Subject: Re: bus_dma and cache line sizes
To: Castor Fu <email@example.com>
From: Nathan J. Williams <nathanw@MIT.EDU>
Date: 03/25/2000 02:20:48
<firstname.lastname@example.org> (Castor Fu) writes:
> The QED5231 processor has a 32-byte cache line size,
> and the tulip family uses a 16-byte (or more) descriptor.
> This leads to the following race condition:
> 1. processor reads a descriptor in the
> second half of a cache line to
> begin updating it.
> 2. enet chip writes a descriptor in the
> first half a cacheline indicating
> it's done with it.
> 3. processor writes out the descriptor,
> trashing the data written in .
> The two obvious solutions are to access the descriptors
> as uncached memory, or I need to know the cache line size to
> pad the descriptors to 32 bytes. Any suggestions
> on what "The Right Thing" is?
Isn't it usually the responsibility of the cache and memory
controllers to keep the cache coherent with memory in the presence of
DMA (or multiprocessing)? Why isn't that happening here?