Subject: bus_dma and cache line sizes
To: None <firstname.lastname@example.org>
From: Castor Fu <email@example.com>
Date: 03/24/2000 18:00:55
I ran into a problem with the tulip driver on a mips platform
where the machine-independent solution is not clear to me, so I
figured I should bounce it off of tech-kern.
The QED5231 processor has a 32-byte cache line size,
and the tulip family uses a 16-byte (or more) descriptor.
This leads to the following race condition:
1. processor reads a descriptor in the
second half of a cache line to
begin updating it.
2. enet chip writes a descriptor in the
first half a cacheline indicating
it's done with it.
3. processor writes out the descriptor,
trashing the data written in .
The two obvious solutions are to access the descriptors
as uncached memory, or I need to know the cache line size to
pad the descriptors to 32 bytes. Any suggestions
on what "The Right Thing" is?