Subject: Re: spl0() clarification
To: None <email@example.com>
From: Jason R Thorpe <firstname.lastname@example.org>
Date: 03/13/2000 22:08:30
On Sun, Mar 12, 2000 at 10:17:06PM -0800, Ethan Solomita wrote:
> Easy question: if you're at a spl which has interrupts disabled, should
> spl0() enable them? I would think so, but the MIPS port is a little
> diferent. With MIPS, there are bits to block each individual interrupt
> line, but there's also a single bit to enable/disable them all.
What spl0() should do is not set the global enable, but rather unblock
any that may be blocked.
This is how the x86 port works, for example. The global interrupt enable
is done separately with cli/sti.
> Any opinions on whether spl0() should, at the same time it enables all
> the individual interrupt lines, should also set the overall-enable bit?
> Given that there's no other standard mechanism in place that would
> enable it.
You should probably use a separate mechanism for the global interrupt
enable. It would be okay, however, to use the global enable bit in the
critical section of cpu_switch as an optimization. Again, the x86 port
already does this.
> The context of my question is that I have a kernel thread, which seems
> to be created at splhi() (which seems strange and could form another
> question in and of itself). Since I have never been at a lower spl to
> splx() back to, the only way to lower my priority seems to be a spl0().
> But it doesn't actually set the enable-interrupts bit, so it isn't
Which kernel thread is this? Note that the global interrupt enable should be
set at the end of cpu_configure(); no kernel threads should be created until
that function returns.
-- Jason R. Thorpe <email@example.com>