Ethan Solomita wrote: 
|  	Easy question: if you're at a spl which has interrupts disabled, should
|  spl0() enable them? I would think so, but the MIPS port is a little
|  diferent. With MIPS, there are bits to block each individual interrupt
|  line, but there's also a single bit to enable/disable them all.
|  
|  	Any opinions on whether spl0() should, at the same time it enables all
|  the individual interrupt lines, should also set the overall-enable bit?

spl0 semantics have "always" been that it enables all interrupts,
regardless of the underlying mechanism.

However, the seperate enable/disable instructions on some architectures
are usually used for very short periods around critical sections that
occur frequently enough that you want to minimize their cycle count,
and therefore spl0 shouldn't be doing anything with those bits.

Correspondingly, splhi() shouldn't be touching those instructions/enable bits
either (except perhaps briefly while doing setup).

If our splhi() is disabling interrupts, that's broken.