Subject: Re: 32-bit+ addressing (was Re: savecore_flags="-z")
To: Colin Wood <>
From: Jonathan Stone <jonathan@DSG.Stanford.EDU>
List: tech-kern
Date: 12/02/1999 16:58:50
In message <>
Colin Wood writes:

>Jonathan Stone wrote:
>read section 3.8 of vol 3 of the intel architecture software developer's
>manual.  [...]

Read it *again*? Surely it hasn't changed that much from the
Pentium Pro edition, physical address limits aside?

Thanks for the pointer to the Intel docs, but that wasn't quite what I
was asking.  Imagine all the PTE issue with large pages are fixed in
the i386 pmap: what then?

(if it helps, imagine the question is coming from someone familiar
with Unix on PDP-11s with larger physical addresses than
virtual. Someone who's already hacked two or three OSes to use giant
pages to access framebuffers, to reduce TLB thrashing.  And someone
familiar with the i386 pte issues: a couple of years back, I frobbed
my own NetBSD/i386 tree to use the cache-control bits in the PTEs to
tune for gigabit NICs, and toyed with using the large-page PTEs.)

For NetBSD/i386, assuming PCI memory space == physical memory space is
one gotcha. Certainly once you get past 4GB, perhaps earlier,
depending on how PCI space gets mapped into the system physical
address space. I have no clue what other assumptions (implicit or
explicit) might get violated (or even if anyone else has really
thought it all through, either.)

Apologies if that was unclear.