Subject: Re: pageable kernel pmap entries
To: Jonathan Stone <jonathan@DSG.Stanford.EDU>
From: Jason Thorpe <firstname.lastname@example.org>
Date: 05/03/1999 16:21:34
On Mon, 03 May 1999 16:12:09 -0700
Jonathan Stone <jonathan@DSG.Stanford.EDU> wrote:
> Why, given that it has a significant runtime cost, do we need it in
> the first place?
(1) Chuq needs it to work properly for the unified buffer cache
he's been working on.
(2) It would be nice to be able to page out parts of the kernel
address space when they're not needed (e.g. some types of
pool pages, etc.)
Perhaps you're confusing `wired == TRUE' in the pmap_enter() sense with
Wired (Safe) TLB entires in MIPS terminology.
From my study of the MIPS pmap (something I've looked at QUITE extensively
in the past 2 weeks, while rewriting large parts of it), the `wired'
parameter to pmap_enter() sets only a SOFTWARE bit in the PTE, which
is ignored when the PTE is loaded in the Lo portion of the TLB.
In other words, it has no correlation to the MIPS Safe TLB entries, nor
should it; those TLB entries are in short supply, and really only ought
to be used for mapping the kernel stack (which is, in fact, what they
are currently used for). `wired' in the VM system means "may not cause
a page fault". This is NOT the same as "may not cause a TLB miss". On
many architectures, you simply have NO WAY to guarantee the latter!
I'm curious why you even brought up the issue on the Alpha. The Alpha,
from the kernel programmer's perspective, has no Safe TLB entries like
the MIPS; `wired' is a purely software notion, as far as the kernel knows.
Yes, the Alpha is a pure TLB like the MIPS is, and probably has such Safe
TLB entries, but it's all abstracted by PALcode into a 3-level page table,
so it's not like the issue you seem to be raising exists on the Alpha,
contrary to what you apparently believe.
-- Jason R. Thorpe <email@example.com>