Subject: Re: pageable kernel pmap entries
To: None <email@example.com>
From: Chuck Silvers <firstname.lastname@example.org>
Date: 04/29/1999 10:26:54
"Eduardo E. Horvath" writes:
> On Thu, 29 Apr 1999, Chuck Silvers wrote:
> > one bit of separable work that'll be needed for the merged buffer/page cache
> > stuff is pageable kernel pmap entries, which are not implemented on at least
> > the sparc port (both sun4c and sun4m). some of the other pmap modules
> > are pretty opaque to me so there might be others that need work.
> What do you mean by `pageable kernel pmap entries'? Do you plan to page
> out parts of the kernel pmap? Why is this a requirement for the merged
> buffer/page cache stuff?
the idea is that you leave as much of the cached data mapped in the kernel
as you can, and the obvious way to do that is with pageable (ie. "non-wired")
pmap entries. then the mappings to cached file data compete with everything
else for pmegs on the sun4c and sun3. I don't know how other ports will
want to deal with this. pagetable-based MMUs probably don't care so much...
the only difference there is that you could reclaim the PTPs for these
mappings, which may not be worth it, depending on how much virtual space
you use for the mapping cache.
in general, with UBC there can be a lot more kernel mappings than there
are now, and the UBC mappings don't need to be wired so there's some room
to play games with how we manage them.