Hi folks,

OK I have tried a few things now.
I tried to move our Cumana driver to the MI driver. To get this kernel
compiled and linked I had to:
-Make ncr53c9x_readregs() usable outside the MI driver.
-*Disable the NCR_NODMA stuff added to the private NCR driver as the MI driver
 doesn't have it.*
For now, I ignored the sc_features variable in the ncr53c9x_softc struct. The
Amiga drivers I looked at also didn't change it.

But this kernel goes crazy. When trying to probe the devices attached to the
SCSI bus, I get errors like "sync nego not completed!", "mode sense(4)
returned nonsense" etc. I don't know how exactly they read because further
errors are reported for all devices so everything scrolls by quickly.

So I went back to the private NCR driver and tried to disable the NCR_NODMA
stuff as well. Then it goes crazy in the same way as the MI driver! So I
conclude that my only problem moving to the MI driver are these two changes
made in the private copy of ncr53c9x.c to get PIO working:

In ncr53c9x_msgout():
	if ((sc->sc_flags & NCR_NODMA) == 0) {
		/* (re)send the message */
		size = min(sc->sc_omlen, sc->sc_maxxfer);
		NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
		/* Program the SCSI counter */
		NCR_WRITE_REG(sc, NCR_TCL, size);
		NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
		if (sc->sc_cfg2 & NCRCFG2_FE) {
			NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
		}
		/* load the count in */
		NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);
		NCRCMD(sc, NCRCMD_TRANS|NCRCMD_DMA);
		NCRDMA_GO(sc);
	}
	else
	{
		int i;
		for (i = 0; i < sc->sc_omlen; i++)
			NCR_WRITE_REG(sc, NCR_FIFO, sc->sc_omess[i]);
NOTE: This used to be FIFO, but I think   ^^^^^^^^ this was only a flag that
got set in the kernel config file. When this was removed, this failed to
compile so I changed it to NCR_FIFO.
		NCRCMD(sc, NCRCMD_TRANS);
		sc->sc_omlen = 0;
	}
}

In ncr53c9x_intr():
		setup_xfer:
			/* Target returned to data phase: wipe "done" memory
*/
			ecb->flags &= ~ECB_TENTATIVE_DONE;

			/* Program the SCSI counter */
			NCR_WRITE_REG(sc, NCR_TCL, size);
			NCR_WRITE_REG(sc, NCR_TCM, size >> 8);
			if (sc->sc_cfg2 & NCRCFG2_FE)
				NCR_WRITE_REG(sc, NCR_TCH, size >> 16);
			/* load the count in */
			NCRCMD(sc, NCRCMD_NOP|NCRCMD_DMA);

			/*
			 * Note that if `size' is 0, we've already
			 * transceived all the bytes we want but
			 * we're still in DATA PHASE.  Apparently,
			 * the device needs padding. Also, a
			 * transfer size of 0 means "maximum" to
			 * the chip DMA logic.
			 */
			if((sc->sc_flags & NCR_NODMA) == 0) {
			{
				NCRCMD(sc,
				(size==0?NCRCMD_TRPAD:NCRCMD_TRANS)|NCRCMD_DMA
);
			} 
			NCRDMA_GO(sc);
/*			printf("NCRDMA_GO() returned\n");*/
			return 1;


Mark, what do you mean with "this can be implemented within the DMA frame
work of the driver"?

Michael, you said you had a driver using the MI driver that only does PIO.
Can you tell me how to set this up?  
-- 
So long, Markus

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my homepage at http://www.gp.fht-esslingen.de/students/emw4maba