>[ With any luck, this message will actually make it out to the world.  The
>  network problems at MAE West are becoming a ... large source of annoyance
>  for me right now. ]

Yup.

>On Sun, 1 Feb 1998 05:06:45 -0800 (PST) 
> Ross Harvey <ross@teraflop.com> wrote:
.
> > I do want to state for the record that I think bus_dma(9) is a work
> > of exceptional merit, and that I will continue to hold that opinion
> > even if BUS_DMAMEM_NOSYNC is allowed to live.
>
>Heh, thanks :-)  Given some comments from Jonathan Stone, I think I
>may indeed allow it to live, but in a slightly different way; see below.


Looks great to me, but then it's prety much exaclty what I suggested.
I like the namechange and you got the motivation about cache-coherence
of DMA pretty much right.  I'd buy this and I hope Matt Thomas will,
too.

Mmm, if it's relevant, don't forget to acknowledge the people who
yelled and screamed, er, offered constructive criticism to the
bus-space and bus-dma work, specially all the changes since the NetBSD
1.2 version of bus spaces... (those separate io and mem spaces?)

>            Synchronization operations are expressed from the perspective
>            of the host RAM, e.g. a device -> memory operation is a READ,
>            and a memory -> device operation is a WRITE.


The only quibble I have is that i find this completely
counterintuitive. The Hardware designers I debug hardware for
consistently use "DMA read" to mean a read request from the device to
memory -- an output operation -- and "DMA write" to mean an input
operation.  Mixing "DMA" and READ|WRITE together seems like an RSVPed
invitation to confusion.


Hmmmmmm.... oops. Jason, is there an implicit bus-space barrier
operation (or moral equivalent) in doing a DMA-synch operations on a
BUS_DMA_COHERENT dma map? I think there really needs to be, to get the
desired effect. (I'm thinking writebuffer drain here, rather than DMA
consistency per se).

Otherwise, driver writers would have to put one in, there might not be
a bus-space tag handy, it's ugly, and it's suboptimal in the case
where a DMA_COHERENT mapping wasn't available.

Is that clear or is a concrete example needed?