On Thu, 14 Aug 1997, Jason Thorpe wrote:

> That is incorrect.  There _are_ explicit alignment constraints on the
> read/write multi/region methods.

Then the docs need to be modified/improved.  What I read is that alignment
`may' be required, and writers of MI drivers `should' be aware that the
bus may have alignment constraints.  In other words, the documentation
contains explicit warnings and recommendations, not requirements.  Perhaps
the words `shall' and `must' could be used for greater clarity in the
instances that warrant it?

> For some busses, the only sane way to treat them is their "native" byte
> order.  I.e. ISA, EISA, and PCI should all be considered "little endian".
> It's my opinion that the bus_space_* functions _should_ perform the
> necessary byte swapping, and the components on boards should always
> be configured for the byte order they'd be configured if the processor
> were little-endian.

This is a great idea, except for the hardware that is wired contrarily.
I'm glad I don't have to deal with any of those strange ISA bridges in
other 68K-based systems. :-)

--scott