On Thu, 13 Mar 1997, Gordon W. Ross wrote:

> > On some machines it is quite possible that the physical address exceeds
> > the size of the virtual address space.  As mentioned above, the SPARC v8
> > physical address logically includes an 8-bit ASI (address space
> > identifier) which means that they have a 40-bit physical address, but
> > 32-bit virtual addresses.
> 
> I'm aware of that.  How large is a page-table entry?
> If a PTE fits in a long, then d_map could return a PTE.
> (pmap_enter gets a PTE as the "pa" argument)

There are no PTEs.  A TLB entry consist of two 64-bit entities: a TLB tag
and a TLB data entry.  The tag contains VA and context info.  The TLB data
is the equivalent of a PTE with the physical address and protection bits.  

There is H/W support to automatically generate addresses for a TSB that is
a direct mapped cache for TLB entries.  Each TSB consists of a 64-bit tag
and 64-bit data fields.  Although it is sometimes nice to pass around the
TSB tag fields, it is not necessary.

As a small aside, it would be really nice if the pmap subsystem could get
access to vm_maps and vm_page structures.  Then the TLB data entry could
be stored in the vm_page structure and some aspects of pmap could be
simplified.  This all leads into the question of how to efficiently deal
with processes that have 64-bit virtual address spaces....

=========================================================================
Eduardo Horvath				eeh@btr.com
"Cliffs are for climbing.  That's why God invented grappling hooks."
					- Benton Frasier