Subject: Re: splraise?
To: None <leo@ahwau.ahold.nl, thorpej@nas.nasa.gov>
From: Chris Torek <torek@BSDI.COM>
List: tech-kern
Date: 03/05/1997 16:09:41
Actually, there are (well, `were' when I checked BSD/OS) only two
spl's (three if you count splx) that *enable* interrupts:

	splsoftclock: used in hardclock to handle softclock without
	a softint.

	spl0: enable all interrupts.

If you simply think of all other splN's as `raise IPL to at least N',
everything should work out.

I actually think that the splsoftclock in hardclock should be
renamed, except that I cannot think of a good name, and then
define spl[a-z]+ as `block the given interrupts', spl0 as
`open the floodgates', and splx as, well splx.  (Okay, so splx
matches the spl[a-z]+ pattern, but you know what I mean. :-) )

Chris