Subject: Re: Proposal for generalized MI soft interrupts
To: Charles M. Hannum <firstname.lastname@example.org>
From: Bill Studenmund <email@example.com>
Date: 01/30/1997 14:39:54
> firstname.lastname@example.org (Bill Studenmund) writes:
> > 2) How would such a setup relate to an SMP system?
> In my world, spl*() will eventually go away completely. But we're not
> ready for that yet, and I need this particular problem solved ASAP.
Ok. This change sounds good, especially if it can be rigged s.t.
the soft interrupts could run at below spl1(). The mac68k port looses
clock ticks at spl1, and keeping spltty and splsoftnet somewhere
between spl0() and spl1() would help.
Oh, one question about IPL_SOFTSERIAL being higher than IPL_SOFTNET,
shouldn't they be the same level? I thought the main use of
these levels was to restrict access to certain personality
structures (like struct tty) and to lock access to the queues.
If these things are at different levels and you were in the middle
of dealing with a ppp packet (at SOFTNET), is there any way the
SOFTSERIAL side of the ppp line discipline code could get called,
which would then try to dork with the ppp packet queue, which the
SOFTNET was trying to prevent. Or am I missing something?