Subject: Re: i386 interrupt counters
To: Noriyuki Soda <email@example.com>
From: Chris G Demetriou <Chris_G_Demetriou@ux2.sp.cs.cmu.edu>
Date: 08/15/1996 17:18:48
> > In "my little world," the right thing is to e.g. have ISA IRQ lines
> > associated with their bus, i.e.:
> > isa0 irq 0
> [ ... ]
> > isa0 irq 1
> > etc.
> > That opens the possibility for multiple ISA busses in a given machine
> How about this (on i386) ?
> mainbus0 irq 0
> mainbus0 irq 1
That could make sense. However, i'd go with 'isa' because the PICs
are an ISA thing, because PCI interrupts really are routed through
them, and because you always have an ISA bus.
> Theoretically, it is possible that devices which are attached on
> different buses (eg. pci0 and pci1, pci0 and eisa0) share same
> interrupt line. Though I don't know whether such a machine really
> exists or not.
Actually, that's not only possible, but on the i386 not particularly
unlikely to happen. (Certainly, the only thing preventing it is
BIOS and setup software.)
Given the way that PCI interrupt mapping works, it's not at all
unlikely that, say, devices on pci0 would map to the same interrupt
lines as devices on pci1 (assuming the pci1 is a secondary bus hanging
off of pci0), etc.