% > : spl is probably fundamentally wrong for SMP.  I haven't thought much
% > : about what to use instead.
% > 
% > The Solbourne people might disagree with you.  As might the VMS
% > Digitial people.  Both groups used a scheme where you would raise the
% > spl *AND* grab access locks to data structures (I think the latter was
% 
% It's the quick and dirty route to getting an SMP version out the door
% under budgetary or market timing constraints. 
% 
% To do it right, sections of code have to be rewritten to make the code as
% parallel as possible. 
% 
% Caching also works very differently with multiple CPU's.

unless you redesign the interrupt mechanism, you still have to
raise spl levels for locks on data structures that can be accessed
from interrupt handlers (or timeouts etc).  if the cpu runs at the
normal spl, it may end up taking an interrupt and then trying to
lock a structure that the interrupted thread on the cpu had already
locked.

jan-simon.