Subject: Re: ISA bounce buffer/DMA interface
To: "Matt Thomas <matt@lkg.dec.com>
From: Jonathan Stone <jonathan@dsg.stanford.edu>
List: tech-kern
Date: 09/15/1995 17:06:13
>Myself, I'd rather have something:
>
>        db = dma_alloc(bus_pointer);    /* ISA, PCI, QBUS,
>                                           EISA, SBUS, TC, whatever */
>
>        /*
>         * this needs to be a loop in case we cross a page boundary.
>         */
>        do {
>            if (!dma_map(db, &va1, &length1, &bus_addr))
>                goto cleanup;
>            /* use value of bus_addr; va1 & length1 have been modified 
>             * to either NULL & 0 or the amount in the next page */
>        } while (va1 != NULL);
>
>        /*
>         * do it for next virtually discontigous chunk
>         */

As I'm sure Matt and cgd are aware, NetBSD runs pmaxes and Alphas.  At
least the pmaxes have only one mapping register for each device
attached through an IO ASIC. The ASIC interrupts the CPU just before
DMA crosses a page boundary, and it's up to the interrupt handler to
reload the DMA mapping registers for the new page.  I don't know if
TC Alpha IOASIC DMA works the same way or not; for now I'll assume
it does.

I don't understand how to match this DMA model to the to the ISADMA
interface, and I'd really rather not propagate another interface.
I've also started to clean up the disconnect-capable ASC (53c9x)
driver in the pmax to be machine-independent.


It may well be best to handle DEC IO ASIC-style DMA mappings in a
DMA-pointer-change interrupt handler, and not expose them to this
layer of software at all.  I'd appreciate comments either way.