> 
> 
> In  <199508280906.LAA04574@outside.enea.se> , you wrote:
> 
> > Have anyone had a look at those nasty 'whatchouts' that one
> > get with write-back caches and 'direct' dma?
> 
> That really depends on the architecture of the system.  Alpha
> and most Intel platforms perform coherent DMA so this isn't an
> issue.  MIPS (port pmax) does not have coherent DMA and so the
> driver is responsible for using either non-cached memory or is
> responsible for making sure the cache is flushed on DMA operations.

It is no problem to flush caches when one knows a dma operation is
coming up. And right, systems with working cache snooping doesn't
have to bother. So the above is not a 'problem'. And pmaxe's has,
from what i know, write through caches.
> 
> > What i think about is, for instance, the small data structures
> > used in the scsi drivers for reading sense data etc. There is
> > a potential problem with these structures if they share cache
> > lines with data used by the driver or other code.
> 
> If the are small, then the best solution might to allocate them
> out of non-cached memory (for those system without coherent
> DMA implementations).

You are probably right here. Even if it doesn't have to be uncached
but aligned to cache lines. But that's up to the driver. Hmm..
>