Subject: Re: Writeback cache issues
To: Per Fogelstrom <email@example.com>
From: Matt Thomas <firstname.lastname@example.org>
Date: 08/28/1995 08:56:51
In <199508280906.LAA04574@outside.enea.se> , you wrote:
> Have anyone had a look at those nasty 'whatchouts' that one
> get with write-back caches and 'direct' dma?
That really depends on the architecture of the system. Alpha
and most Intel platforms perform coherent DMA so this isn't an
issue. MIPS (port pmax) does not have coherent DMA and so the
driver is responsible for using either non-cached memory or is
responsible for making sure the cache is flushed on DMA operations.
> What i think about is, for instance, the small data structures
> used in the scsi drivers for reading sense data etc. There is
> a potential problem with these structures if they share cache
> lines with data used by the driver or other code.
If the are small, then the best solution might to allocate them
out of non-cached memory (for those system without coherent
> The issue here is that the entire cacheline must be "owned"
> exclusively by the dma or the cpu(cache).
Unless you never let it be in the cache is the first place.
Matt Thomas Internet: email@example.com
3am Software Foundry WWW URL: <currently homeless>
Westford, MA Disclaimer: Digital disavows all knowledge
of this message