Hi!

Have anyone had a look at those nasty 'whatchouts' that one
get with write-back caches and 'direct' dma?

What i think about is, for instance, the small data structures
used in the scsi drivers for reading sense data etc. There is
a potential problem with these structures if they share cache
lines with data used by the driver or other code.

The issue here is that the entire cacheline must be "owned" 
exclusively by the dma or the cpu(cache).


Per