> On RISC processors, there is significant overhead in saving floating
> point registers during a context switch.  To avoid this a kernel will
> often start a process with the FPU disabled and then wait for a
> FPU-disabled exception before enabling it.  In the case of NetBSD, the
> ```printf()''' function contains floating point code which (for one
> architecture at least) results in the compiler generating instructions
> to save floating point registers on function entry (and thus gain the FP
> state) even if the fp code proper is actually never reached.
> 
> Has any one looked into this? (If it makes sense :-)

I've thought about it, but (given my hardware situation, mostly; i'm
stuck having only alphas... 8-) have been unable to come up with any
_numbers_ that show how much of a cost this really is...

I'd definitely like to see such numbers, for a couple of different
processors, before this was jumped into.


chris