Subject: Re: NAND flash support
To: None <firstname.lastname@example.org>
From: Bucky Katz <email@example.com>
Date: 03/12/2007 11:19:39
"Toru Nishimura" <firstname.lastname@example.org> writes:
> David Young email@example.com wrote;
>> Once there are drivers for two or more NAND chips in NetBSD, we can
>> extract the functions that the drivers have in common and produce a
>> NAND framework.
> Let's go in a smart way. I realized L* MTD is not a good example after all
> when I started NAND block device code.
> There are number of ways to control NAND chip;
> 1. bare GPIO fiddling,
> 2. ALE / CLE by address control signal,
> 3. dedicated HW supports by SoC. The simplest is to have extra wires
> to replace GPIOs. The most sophisticated one can perform DMA xfer
> with automatic ECC generation and verification. We can see the wide
> variety of NAND circuit support in modern SoC; Toshiba TX49, AMCC
> PPC440, MesDigital MMSP2, Sharp LH and a flock of other ARM7/9 SoC.
There is also a wide variety of NAND part protocols and, currently, an
attempt to standarize the protocols by the parts vendors.
512 byte nand parts tend to have different protocols than 2k byt nand
parts and all are different than Samsung's OneNand.
Also, existing commercial FTL products make specific demands on NAND
I have implemented a NAND driver as an MI part and device specific
part for NetBSD, but have not submitted it to current yet. I'd like
to propose it as a model. If there's interest, I'll clean it up and
post it for discussion.