Subject: Re: Re(4): Port to 8xx embedded PPCs
To: None <firstname.lastname@example.org, email@example.com>
From: Randy Devol <firstname.lastname@example.org>
Date: 06/20/2000 09:52:14
| On Mon, Jun 19, 2000, Ignatios Souvatzis <email@example.com> wrote:
| >> Regarding the kernel, the MMU is different, so all the memory management
| >> stuff need probably a complete rewrite.
| >how different is it, exactly?
| It has only TLBs, no hash table (a bit like the 603 but the TLBs and
| exception mecanisms are different). It provides a different set of
| special registers for use in those exceptions (TLB reload). The number of
| TLBs can be different between processor models. That's all I know for
| now, I didn't dive in the manual yet. But for example, linux/ppc uses
| completely different exception handlers for TLB reloads than it uses for
| 604-like (hash table based) or 603-like (TLB only) CPUs.
The 8xx TLBs are rather like 680x0 TLBs. They are designed for reloading
from two-level tables in RAM. Suffice it to say that almost no MMU code can
be shared between the existing PPC port(s) and a new 8xx port.
BTW, I am most of the way through a port but have had to take time off to pay
bills. The work I have done to date is not available for free, but it is
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