Subject: CVS commit: src/sys/arch/sgimips/sgimips
To: None <>
From: Christopher SEKIYA <>
List: source-changes
Date: 03/01/2005 04:25:00
Module Name:	src
Committed By:	sekiya
Date:		Tue Mar  1 04:25:00 UTC 2005

Modified Files:
	src/sys/arch/sgimips/sgimips: machdep.c

Log Message:
Set mips_sdcache_forceinv to 1 for r5k processors.

We now support secondary cache operation on r5ksc out-of-the-box.

To generate a diff of this commit:
cvs rdiff -r1.89 -r1.90 src/sys/arch/sgimips/sgimips/machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.