Subject: CVS commit: src/sys/arch/mips
To: None <>
From: Christopher SEKIYA <>
List: source-changes
Date: 03/01/2005 04:23:44
Module Name:	src
Committed By:	sekiya
Date:		Tue Mar  1 04:23:44 UTC 2005

Modified Files:
	src/sys/arch/mips/include: cache.h
	src/sys/arch/mips/mips: cache.c pmap.c

Log Message:
Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.

This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.

This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.

To generate a diff of this commit:
cvs rdiff -r1.6 -r1.7 src/sys/arch/mips/include/cache.h
cvs rdiff -r1.25 -r1.26 src/sys/arch/mips/mips/cache.c
cvs rdiff -r1.156 -r1.157 src/sys/arch/mips/mips/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.