Subject: CVS commit: src/sys/dev/pci
To: None <source-changes@NetBSD.org>
From: Allen Briggs <briggs@netbsd.org>
List: source-changes
Date: 06/23/2004 14:40:13
Module Name:	src
Committed By:	briggs
Date:		Wed Jun 23 14:40:13 UTC 2004

Modified Files:
	src/sys/dev/pci: satalink.c

Log Message:
When the Silicon Image 3112 retries a PCI memory read command, it
may retry it as a memory read multiple command under some circumstances.
This can totally confuse some PCI controllers, so ensure that it
will never do this by making sure that the Read Threshold (FIFO
Read Request Control) field of the FIFO Valid Byte Count and Control
registers for both channels (BA5 offset 0x40 and 0x44) are set to
be at least as large as the cacheline size register (the unit of
measure for these registers is 32 bytes).


To generate a diff of this commit:
cvs rdiff -r1.15 -r1.16 src/sys/dev/pci/satalink.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.