Module Name:	src
Committed By:	thorpej
Date:		Tue Apr 22 00:24:50 UTC 2003

Modified Files:
	src/sys/arch/arm/arm: cpufunc.c
	src/sys/arch/arm/arm32: cpuswitch.S genassym.cf pmap.c pmap_new.c
	    vm_machdep.c
	src/sys/arch/arm/include: cpuconf.h
	src/sys/arch/arm/include/arm32: pmap.h
	src/sys/arch/shark/conf: GENERIC

Log Message:
Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1.  While the SA-1's MMU is basically
  compatible with the generic, the SA-1 cache does not have a write-through
  mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
  compile time.  We evaluate it like so:
  - If SA-1-style MMU is the only type configured -> 1
  - If SA-1-style MMU is not configured -> 0
  - Otherwise, defer to a run-time variable.
  If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
  check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
  code can include the necessary run-time support.  PMAP_INCLUDE_PTE_SYNC
  largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
  included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
  has a write-back cache.  If so, init the PT cache mode to C=1,B=0 to get
  write-through mode.  Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8().  Old pmap, same as generic.  New pmap,
  sets page table cacheability to 0 (ARM8 has a write-back cache, but
  flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
  C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
  since we use write-through mode all the time on ARM9 right now.  (What
  this really tells me is that the test for write-through cache is less
  than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1().  Old pmap, same as generic.  New pmap,
  does generic initialization, then resets page table cache mode to
  C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.


To generate a diff of this commit:
cvs rdiff -r1.57 -r1.58 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -r1.30 -r1.31 src/sys/arch/arm/arm32/cpuswitch.S
cvs rdiff -r1.22 -r1.23 src/sys/arch/arm/arm32/genassym.cf
cvs rdiff -r1.130 -r1.131 src/sys/arch/arm/arm32/pmap.c
cvs rdiff -r1.3 -r1.4 src/sys/arch/arm/arm32/pmap_new.c
cvs rdiff -r1.26 -r1.27 src/sys/arch/arm/arm32/vm_machdep.c
cvs rdiff -r1.5 -r1.6 src/sys/arch/arm/include/cpuconf.h
cvs rdiff -r1.68 -r1.69 src/sys/arch/arm/include/arm32/pmap.h
cvs rdiff -r1.14 -r1.15 src/sys/arch/shark/conf/GENERIC

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.