Module Name:	syssrc
Committed By:	thorpej
Date:		Fri Jan 25 21:33:26 UTC 2002

Modified Files:
	syssrc/sys/arch/arm/arm: cpufunc.c

Log Message:
* Default dcache_inv_range to xscale_cache_flushD_rng for XScale
  cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
  xscale_cache_purgeD_rng to work around a bug where a D$
  "invalidate by address" doesn't properly clear the dirty
  bits on the cache block (i80200 errata item #25).


To generate a diff of this commit:
cvs rdiff -r1.27 -r1.28 syssrc/sys/arch/arm/arm/cpufunc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.