Subject: CVS commit: syssrc/sys/arch/arm/arm32
To: None <>
From: Richard Earnshaw <>
List: source-changes
Date: 10/18/2001 20:06:14
Module Name:	syssrc
Committed By:	rearnsha
Date:		Thu Oct 18 17:06:14 UTC 2001

Modified Files:
	syssrc/sys/arch/arm/arm32: pmap.c

Log Message:
On processors that support both write-through and write-back cacheing
(eg ARM920), the mode in which the processor operates is governed by
the use of both the PT_C and PT_B bits:

	PT_C=1,PT_B=1 -> Write-back
	PT_C=1,PT_B=0 -> Write-through

To support this define pte_cache_mode (initialized to PT_C|PT_B) and
use that when enabling cacheing for a page.

To generate a diff of this commit:
cvs rdiff -r1.26 -r1.27 syssrc/sys/arch/arm/arm32/pmap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.