Subject: Re: CVS commit: syssrc
To: Izumi Tsutsui <email@example.com>
From: Matthew Jacob <firstname.lastname@example.org>
Date: 02/24/2001 01:10:05
On Sat, 24 Feb 2001, Izumi Tsutsui wrote:
> In <Pine.BSF.email@example.com>
> firstname.lastname@example.org wrote:
> > You don't need a preread because the CPU never writes the response queue- only
> > the device. The man page says:
> > Synchronization operations are expressed from the perspective of
> > the host RAM, e.g. a device -> memory operation is a READ and a
> > memory -> device operation is a WRITE.
> > Ergo, after the ISP writes the response queue a BUS_DMASYNC_POSTREAD sync
> > is done to synchronize the CPU's view of the response queue.
> The implementation of cache operations in
> bus_dmamap_sync() is completely machine dependant.
> In some CPU (like mips with current implementation),
> all flush operations are done only in BUS_DMASYNC_PRE* case.
> If your CPU can invalidate cache without writeback data to memory,
> cache flush could be done on BUS_DMASYNC_POSTREAD.
> But if invalidation also causes data writeback,
> it should be done on BUS_DMASYNC_PREREAD.
But you need a hint to know that a particular piece of memory is to be treated
coherent or not.
> PREREAD might be no-op on some archs,
> but it should not be omitted in MI code.
> > The last checkin uncommented the #if 0 around such a BUS_DMASYNC_POSTWRITE.
> Do you mean bus_dmamap_sync() in isp_sbus_dmasetup() ?
> It is BUS_DMASYNC_PREWRITE, not POSTWRITE.
> Anyway POSTWRITE is provided only for consistency (unlike PREREAD).
> Izumi Tsutsui