Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Tue Dec 19 18:53:52 UTC 2000

Modified Files:
	pkgsrc/cad/verilog-current: Makefile
	pkgsrc/cad/verilog-current/files: md5 patch-sum
	pkgsrc/cad/verilog-current/patches: patch-ad
	pkgsrc/cad/verilog-current/pkg: PLIST
Added Files:
	pkgsrc/cad/verilog-current/patches: patch-aa

Log Message:
update verilog-current to 20001216.

Changes since the last packaged snapshot are (from the authors announcements):

Icarus Verilog snapshot 20001216
--------------------------------
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)

I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.

I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.

Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.

I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.

I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.

Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.

Icarus Verilog snapshot 20001129
--------------------------------
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!

Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get
connected.

A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.

Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.

There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.

I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.


To generate a diff of this commit:
cvs rdiff -r1.9 -r1.10 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.9 -r1.10 pkgsrc/cad/verilog-current/files/md5 \
    pkgsrc/cad/verilog-current/files/patch-sum
cvs rdiff -r0 -r1.5 pkgsrc/cad/verilog-current/patches/patch-aa
cvs rdiff -r1.7 -r1.8 pkgsrc/cad/verilog-current/patches/patch-ad
cvs rdiff -r1.6 -r1.7 pkgsrc/cad/verilog-current/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.