Module Name:	syssrc
Committed By:	bjh21
Date:		Sat Dec 16 18:23:14 UTC 2000

Modified Files:
	syssrc/sys/arch/arm26/podulebus: if_ehreg.h

Log Message:
I think bit 0 of the status register is the interrupt status on read.


To generate a diff of this commit:
cvs rdiff -r1.1 -r1.2 syssrc/sys/arch/arm26/podulebus/if_ehreg.h

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