Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Wed Nov 22 21:15:13 UTC 2000

Modified Files:
	pkgsrc/cad/acs: Makefile
	pkgsrc/cad/acs/files: md5
	pkgsrc/cad/acs/pkg: PLIST

Log Message:
update to acs-0.28

from the history file:
----------------------
New features:

1. New probes: diode G, mos IBD, IBS, GBD, GBS.

2. New options: "floor" and "vfloor".  (Floor was in the manual, but
not in the simulator.)

Improvements, bug fixes, etc.

1. There is a change to the way behavioral modeling conditionals are
handled.  It should now be 100% compatible with SPICE, considering the
subset that duplicates SPICE.  There are still significant extensions
beyond SPICE, particularly that you can have behavioral resistors,
capacitors, inductors, etc.

2. Parameter default calculations are now done in a manner consistent
with Spice 3f5.  Previously, it was supposedly consistent with Spice
2g6.

3. A bug in calculation of threshold voltage of the level 6 model, for
P channel devices, has been fixed.

4. A bug in calculation of Meyer capacitances when the device is
reversed has been fixed.  This bug sometimes caused a discontinuity at
vds=0.

5. I have added some smoothing to the Meyer mos capacitor models.
This improves convergence.   The down side is that sometimes the
answers are different.  It is probably a little better, when
considering closeness to reality, but it is still Meyer's model.

6. MOSFET parasitic diodes are now the same as those used in Spice.

7. There are subtle changes in the diode model.  I think this usually
improves convergence.

8. Charge calculation in Meyer capacitors and diode capacitiors is now
supposedly Spice 3 compatible.

9. An error in BSIM3 scaling has been fixed.

Some things that are still partially implemented:

1. Internal element: non-quasi-static poly-capacitor.

2. BSIM models, charge effects.

Bugs (nothing new, but needs repeating):

1. The transmission line initial conditions are not propagated until
the transient analysis runs.

2. The makefile does not set up the proper link for the model
compiler.  You need to do it manually.

3. A bad setting of "vmax" and "vmin" can lead to convergence to a
nonsense result.  It is not as bad now as it used to be.


To generate a diff of this commit:
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/acs/Makefile
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/acs/files/md5
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/acs/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.