Subject: CVS commit: syssrc
To: None <email@example.com>
From: Castor Fu <firstname.lastname@example.org>
Date: 10/24/2000 06:23:20
Module Name: syssrc
Committed By: castor
Date: Tue Oct 24 03:23:20 UTC 2000
In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.
It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.
To generate a diff of this commit:
cvs rdiff -r1.57 -r1.58 syssrc/sys/arch/mips/mips/locore_mips3.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.