Subject: CVS commit: syssrc
To: None <>
From: Tohru Nishimura <>
List: source-changes
Date: 03/26/2000 21:23:43
Module Name:	syssrc
Committed By:	nisimura
Date:		Mon Mar 27 05:23:43 UTC 2000

Modified Files:
	syssrc/sys/arch/mips/include: locore.h
	syssrc/sys/arch/mips/mips: locore_mips1.S mips_machdep.c

Log Message:
- Rename some of TLB ops to have handy abbrivations hired from VAX and
  ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
  which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.

  it's less-than-optimal and likely a mistake to have TLBUpdate().
  It's costy to try to invalidate a single TLB entry whenver a certain
  PTE is going to be modified by traversing the entire TLB looking
  for the modified PTE because the PTE in question is not in TLB in
  most cases.  ASID bump could do the invalidation smartly.  Solution
  is planned for now.

To generate a diff of this commit:
cvs rdiff -r1.26 -r1.27 syssrc/sys/arch/mips/include/locore.h
cvs rdiff -r1.23 -r1.24 syssrc/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -r1.70 -r1.71 syssrc/sys/arch/mips/mips/mips_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.