Subject: NetBSD master CVS tree commits
To: None <source-changes@NetBSD.ORG>
From: None <source@NetBSD.ORG>
List: source-changes
Date: 04/10/1997 23:20:01
cgd
Thu Apr 10 16:10:35 PDT 1997
Update of /cvsroot/src/sys/arch/alpha/conf
In directory netbsd1:/var/slash-tmp/cvs-serv1969

Modified Files:
	ALPHA GENERIC 
Log Message:
enabled EB64+ support

cgd
Thu Apr 10 16:12:19 PDT 1997
Update of /cvsroot/src/sys/arch/alpha/pci
In directory netbsd1:/var/slash-tmp/cvs-serv2214/arch/alpha/pci

Modified Files:
	apecs.c cia.c dwlpx.c lca.c 
Log Message:
pass memory- and i/o-enabled flags down via the PCI bus and device attach
arguments, so that a device can tell if its memory and I/O spaces are
enabled.  The flags are cleared, depending on the contents of devices CSR
registers, in the machine-independent PCI bus code.


cgd
Thu Apr 10 16:12:20 PDT 1997
Update of /cvsroot/src/sys/arch/atari/pci
In directory netbsd1:/var/slash-tmp/cvs-serv2214/arch/atari/pci

Modified Files:
	pci_machdep.c 
Log Message:
pass memory- and i/o-enabled flags down via the PCI bus and device attach
arguments, so that a device can tell if its memory and I/O spaces are
enabled.  The flags are cleared, depending on the contents of devices CSR
registers, in the machine-independent PCI bus code.


cgd
Thu Apr 10 16:12:22 PDT 1997
Update of /cvsroot/src/sys/arch/i386/i386
In directory netbsd1:/var/slash-tmp/cvs-serv2214/arch/i386/i386

Modified Files:
	mainbus.c 
Log Message:
pass memory- and i/o-enabled flags down via the PCI bus and device attach
arguments, so that a device can tell if its memory and I/O spaces are
enabled.  The flags are cleared, depending on the contents of devices CSR
registers, in the machine-independent PCI bus code.


cgd
Thu Apr 10 16:12:24 PDT 1997
Update of /cvsroot/src/sys/dev/pci
In directory netbsd1:/var/slash-tmp/cvs-serv2214/dev/pci

Modified Files:
	pci.c pcivar.h ppb.c 
Log Message:
pass memory- and i/o-enabled flags down via the PCI bus and device attach
arguments, so that a device can tell if its memory and I/O spaces are
enabled.  The flags are cleared, depending on the contents of devices CSR
registers, in the machine-independent PCI bus code.