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[src/trunk]: src/sys/arch/arm/sociox major code quality improvements, descrip...
details: https://anonhg.NetBSD.org/src/rev/0ae59b89a8ec
branches: trunk
changeset: 376352:0ae59b89a8ec
user: nisimura <nisimura%NetBSD.org@localhost>
date: Tue Jun 13 00:15:52 2023 +0000
description:
major code quality improvements, descriptive comments, code density.
diffstat:
sys/arch/arm/sociox/if_scx.c | 306 +++++++++++++++++++++---------------------
1 files changed, 151 insertions(+), 155 deletions(-)
diffs (truncated from 739 to 300 lines):
diff -r 4a6d3fdc3cb0 -r 0ae59b89a8ec sys/arch/arm/sociox/if_scx.c
--- a/sys/arch/arm/sociox/if_scx.c Mon Jun 12 23:29:32 2023 +0000
+++ b/sys/arch/arm/sociox/if_scx.c Tue Jun 13 00:15:52 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $ */
+/* $NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.40 2023/05/21 00:35:38 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.41 2023/06/13 00:15:52 nisimura Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -75,7 +75,7 @@
#include <dev/acpi/acpivar.h>
#include <dev/acpi/acpi_intr.h>
-/* SC2A11 GbE 64-bit paddr descriptor */
+/* SC2A11 GbE has 64-bit paddr descriptor */
struct tdes {
uint32_t t0, t1, t2, t3;
};
@@ -105,8 +105,9 @@ struct rdes {
#define R0_TDRID (12) /* 15:12 target desc ring id */
#define R0_FS (1U<<9) /* first segment of frame */
#define R0_LS (1U<<8) /* last segment of frame */
-#define R0_CSUM (3U<<6) /* 7:6 checksum status */
-#define R0_CERR (2U<<6) /* 0: undone, 1: found ok, 2: bad */
+#define R0_CSUM (3U<<6) /* 7:6 checksum status, 0: undone */
+#define R0_CERR (2U<<6) /* 2: found bad */
+#define R0_COK (1U<<6) /* 1: found ok */
/* R1 frame address 63:32 */
/* R2 frame address 31:0 */
/* R3 31:16 received frame length, 15:0 buffer length to receive */
@@ -120,11 +121,11 @@ struct rdes {
#define INIT_DB (1U<<2) /* ???; self clear when done */
#define INIT_CLS (1U<<1) /* ???; self clear when done */
#define PKTCTRL 0x140 /* pkt engine control */
-#define MODENRM (1U<<28) /* change mode to normal */
+#define MODENRM (1U<<28) /* set operational mode to 'normal' */
#define ENJUMBO (1U<<27) /* allow jumbo frame */
#define RPTCSUMERR (1U<<3) /* log Rx checksum error */
-#define RPTHDCOMP (1U<<2) /* log HD incomplete condition */
-#define RPTHDERR (1U<<1) /* log HD error */
+#define RPTHDCOMP (1U<<2) /* log header incomplete condition */
+#define RPTHDERR (1U<<1) /* log header error */
#define DROPNOMATCH (1U<<0) /* drop no match frames */
#define xINTSR 0x200 /* aggregated interrupt status */
#define IRQ_UCODE (1U<<20) /* ucode load completed; W1C */
@@ -145,16 +146,16 @@ struct rdes {
#define TXIE_SET 0x428 /* bit to set */
#define TXIE_CLR 0x42c /* bit to clr */
#define TXI_NTOWNR (1U<<17) /* ??? desc array got empty */
-#define TXI_TR_ERR (1U<<16) /* tx error */
-#define TXI_TXDONE (1U<<15) /* tx completed */
-#define TXI_TMREXP (1U<<14) /* coalesce timer expired */
+#define TXI_TR_ERR (1U<<16) /* xmit error */
+#define TXI_TXDONE (1U<<15) /* xmit completed */
+#define TXI_TMREXP (1U<<14) /* coalesce guard timer expired */
#define RXISR 0x440 /* receive status; W1C */
#define RXIEN 0x444 /* rx interrupt enable */
#define RXIE_SET 0x468 /* bit to set */
#define RXIE_CLR 0x46c /* bit to clr */
-#define RXI_RC_ERR (1U<<16) /* rx error */
-#define RXI_PKTCNT (1U<<15) /* rx counter has new value */
-#define RXI_TMREXP (1U<<14) /* coalesce timer expired */
+#define RXI_RC_ERR (1U<<16) /* recv error */
+#define RXI_PKTCNT (1U<<15) /* recv counter has new value */
+#define RXI_TMREXP (1U<<14) /* coalesce guard timer expired */
/* 13 sets of special purpose desc interrupt handling register exist */
#define TDBA_LO 0x408 /* tdes array base addr 31:0 */
#define TDBA_HI 0x434 /* tdes array base addr 63:32 */
@@ -163,33 +164,33 @@ struct rdes {
/* 13 pairs of special purpose desc array base address register exist */
#define TXCONF 0x430
#define RXCONF 0x470
-#define DESCNF_UP (1U<<31) /* up-and-running */
+#define DESCNF_UP (1U<<31) /* 'up-and-running' */
#define DESCNF_CHRST (1U<<30) /* channel reset */
#define DESCNF_TMR (1U<<4) /* coalesce timer mode select */
#define DESCNF_LE (1) /* little endian desc format */
#define TXSUBMIT 0x410 /* submit frame(s) to transmit */
-#define TXCLSCMAX 0x418 /* tx intr coalesce upper bound */
-#define RXCLSCMAX 0x458 /* rx intr coalesce upper bound */
-#define TXITIMER 0x420 /* coalesce timer usec, MSB to use */
-#define RXITIMER 0x460 /* coalesce timer usec, MSB to use */
+#define TXCOALESC 0x418 /* tx intr coalesce upper bound */
+#define RXCOALESC 0x458 /* rx intr coalesce upper bound */
+#define TCLSCTIME 0x420 /* tintr guard time usec, MSB to on */
+#define RCLSCTIME 0x460 /* rintr guard time usec, MSB to on */
#define TXDONECNT 0x414 /* tx completed count, auto-zero */
-#define RXDONECNT 0x454 /* rx available count, auto-zero */
+#define RXAVAILCNT 0x454 /* rx available count, auto-zero */
#define DMACTL_TMR 0x20c /* engine DMA timer value */
#define UCODE_H2M 0x210 /* host2media engine ucode port */
#define UCODE_M2H 0x21c /* media2host engine ucode port */
#define CORESTAT 0x218 /* engine run state */
-#define PKTSTOP (1U<<2)
-#define M2HSTOP (1U<<1)
-#define H2MSTOP (1U<<0)
+#define PKTSTOP (1U<<2) /* pkt engine stopped */
+#define M2HSTOP (1U<<1) /* M2H engine stopped */
+#define H2MSTOP (1U<<0) /* H2M engine stopped */
#define DMACTL_H2M 0x214 /* host2media engine control */
#define DMACTL_M2H 0x220 /* media2host engine control */
#define DMACTL_STOP (1U<<0) /* instruct stop; self-clear */
+#define M2H_MODE_TRANS (1U<<20) /* initiate M2H mode change */
#define UCODE_PKT 0x0d0 /* packet engine ucode port */
#define CLKEN 0x100 /* clock distribution enable */
-#define CLK_G (1U<<5) /* feed clk domain E */
+#define CLK_G (1U<<5) /* feed clk domain G */
#define CLK_C (1U<<1) /* feed clk domain C */
#define CLK_D (1U<<0) /* feed clk domain D */
-#define CLK_ALL 0x23 /* all above; 0x24 ??? 0x3f ??? */
/* GMAC register indirect access. thru MACCMD/MACDATA operation */
#define MACDATA 0x11c0 /* gmac register rd/wr data */
@@ -201,7 +202,10 @@ struct rdes {
#define FLOWTHR 0x11cc /* flow control threshold */
/* 31:16 pause threshold, 15:0 resume threshold */
-#define INTF_SEL 0x11d4 /* ??? */
+#define INTF_SEL 0x11d4 /* phy interface type */
+#define INTF_GMII 0
+#define INTF_RGMII 1
+#define INTF_RMII 4
#define DESC_INIT 0x11fc /* write 1 for desc init, SC */
#define DESC_SRST 0x1204 /* write 1 for desc sw reset, SC */
@@ -218,7 +222,7 @@ struct rdes {
* Ethernet. These must be handled by indirect access.
*/
#define GMACMCR 0x0000 /* MAC configuration */
-#define MCR_IBN (1U<<30) /* ??? */
+#define MCR_IBN (1U<<30) /* watch in-band-signal */
#define MCR_CST (1U<<25) /* strip CRC */
#define MCR_TC (1U<<24) /* keep RGMII PHY notified */
#define MCR_WD (1U<<23) /* allow long >2048 tx frame */
@@ -233,7 +237,7 @@ struct rdes {
#define MCR_IPCEN (1U<<10) /* handle checksum */
#define MCR_DR (1U<<9) /* attempt no tx retry, send once */
#define MCR_LUD (1U<<8) /* link condition report when RGMII */
-#define MCR_ACS (1U<<7) /* auto pad strip CRC */
+#define MCR_ACS (1U<<7) /* auto pad auto strip CRC */
#define MCR_DC (1U<<4) /* report excessive tx deferral */
#define MCR_TE (1U<<3) /* run Tx MAC engine, 0 to stop */
#define MCR_RE (1U<<2) /* run Rx MAC engine, 0 to stop */
@@ -404,15 +408,13 @@ struct rdes {
*/
#define _BMR 0x00412080 /* XXX TBD */
-#define _BMR0 0x00020181 /* XXX TBD */
-/* NetSec uses local RAM to handle GMAC desc arrays and frame buffers */
+/* NetSec uses local RAM to handle GMAC desc arrays */
#define _RDLA 0x18000
#define _TDLA 0x1c000
-#define _MCR_FDX 0x0000280c /* XXX TBD */
-#define _MCR_HDX 0x0001a00c /* XXX TBD */
+/* lower address region is used for intermediate frame data buffers */
/*
- * all below are software constraction.
+ * all below are software construction.
*/
#define MD_NTXDESC 128
#define MD_NRXDESC 64
@@ -532,7 +534,7 @@ do { \
bus_addr_t __p = __rxs->rxs_dmamap->dm_segs[0].ds_addr; \
bus_size_t __z = __rxs->rxs_dmamap->dm_segs[0].ds_len; \
__m->m_data = __m->m_ext.ext_buf; \
- __rxd->r3 = htole32(__z); \
+ __rxd->r3 = htole32(__z - 4); \
__rxd->r2 = htole32(BUS_ADDR_LO32(__p)); \
__rxd->r1 = htole32(BUS_ADDR_HI32(__p)); \
__rxd->r0 &= htole32(R0_LD); \
@@ -562,15 +564,15 @@ CFATTACH_DECL_NEW(scx_acpi, sizeof(struc
static void scx_attach_i(struct scx_softc *);
static void scx_reset(struct scx_softc *);
+static void scx_stop(struct ifnet *, int);
static int scx_init(struct ifnet *);
-static void scx_stop(struct ifnet *, int);
static int scx_ioctl(struct ifnet *, u_long, void *);
static void scx_set_rcvfilt(struct scx_softc *);
static void scx_start(struct ifnet *);
static void scx_watchdog(struct ifnet *);
static int scx_intr(void *);
static void txreap(struct scx_softc *);
-static void rxintr(struct scx_softc *);
+static void rxfill(struct scx_softc *);
static int add_rxbuf(struct scx_softc *, int);
static void rxdrain(struct scx_softc *sc);
static void mii_statchg(struct ifnet *);
@@ -580,17 +582,16 @@ static int mii_writereg(device_t, int, i
static void phy_tick(void *);
static void dump_hwfeature(struct scx_softc *);
-static void stopuengine(struct scx_softc *);
-static void startuengine(struct scx_softc *);
+static void resetuengine(struct scx_softc *);
static void loaducode(struct scx_softc *);
static void injectucode(struct scx_softc *, int, bus_addr_t, bus_size_t);
static int get_mdioclk(uint32_t);
-#define WAIT_FOR_SET(sc, reg, set, fail) \
- wait_for_bits(sc, reg, set, ~0, fail)
-#define WAIT_FOR_CLR(sc, reg, clr, fail) \
- wait_for_bits(sc, reg, 0, clr, fail)
+#define WAIT_FOR_SET(sc, reg, set) \
+ wait_for_bits(sc, reg, set, ~0, 0)
+#define WAIT_FOR_CLR(sc, reg, clr) \
+ wait_for_bits(sc, reg, 0, clr, 0)
static int
wait_for_bits(struct scx_softc *sc, int reg,
@@ -616,7 +617,7 @@ mac_read(struct scx_softc *sc, int reg)
{
CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);
- (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0);
+ (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
return CSR_READ(sc, MACDATA);
}
@@ -626,7 +627,7 @@ mac_write(struct scx_softc *sc, int reg,
CSR_WRITE(sc, MACDATA, val);
CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);
- (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY, 0);
+ (void)WAIT_FOR_CLR(sc, MACCMD, CMD_BUSY);
}
/* dig and decode "clock-frequency" value for a given clkname */
@@ -873,7 +874,7 @@ scx_attach_i(struct scx_softc *sc)
uint32_t which, dwimp, dwfea;
uint8_t enaddr[ETHER_ADDR_LEN];
bus_dma_segment_t seg;
- paddr_t paddr;
+ paddr_t p, q;
uint32_t csr;
int i, nseg, error = 0;
@@ -1010,21 +1011,29 @@ aprint_normal_dev(sc->sc_dev, "descripto
rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
RND_TYPE_NET, RND_FLAG_DEFAULT);
- stopuengine(sc);
+ resetuengine(sc);
loaducode(sc);
/* feed NetSec descriptor array base addresses and timer value */
- paddr = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */
- CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(paddr));
- CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(paddr));
- paddr = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */
- CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(paddr));
- CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(paddr));
+ p = SCX_CDTXADDR(sc, 0); /* tdes array (ring#0) */
+ q = SCX_CDRXADDR(sc, 0); /* rdes array (ring#1) */
+ CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
+ CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
+ CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
+ CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */
CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian */
CSR_WRITE(sc, DMACTL_TMR, sc->sc_freq / 1000000 - 1);
- startuengine(sc);
+ CSR_WRITE(sc, DMACTL_M2H, M2H_MODE_TRANS);
+ CSR_WRITE(sc, PKTCTRL, MODENRM); /* change to use normal mode */
+ WAIT_FOR_SET(sc, MODE_TRANS, T2N_DONE);
+ /* do {
+ csr = CSR_READ(sc, MODE_TRANS);
+ } while ((csr & T2N_DONE) == 0); */
+
+ CSR_WRITE(sc, TXISR, ~0); /* clear pending emtpry/error irq */
+ CSR_WRITE(sc, xINTAE_CLR, ~0); /* disable tx / rx interrupts */
return;
@@ -1070,17 +1079,32 @@ scx_reset(struct scx_softc *sc)
} while (++loop < 3000 && busy);
mac_write(sc, GMACBMR, _BMR);
mac_write(sc, GMACAFR, 0);
+}
-#if 0
- CSR_WRITE(sc, CLKEN, CLK_ALL); /* distribute clock sources */
- CSR_WRITE(sc, SWRESET, 0); /* reset operation */
- CSR_WRITE(sc, SWRESET, SRST_RUN); /* manifest run */
- CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS);
- WAIT_FOR_CLR(sc, COMINIT, (INIT_DB | INIT_CLS), 0);
+static void
+scx_stop(struct ifnet *ifp, int disable)
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