[src/trunk]: src/sys/arch/powerpc/fpu Fix priority for NaN propagation: frA >...

[rin <rin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8912bb16b831
branches:  trunk
changeset: 369893:8912bb16b831
user:      rin <rin%NetBSD.org@localhost>
date:      Tue Sep 06 23:04:08 2022 +0000

description:
Fix priority for NaN propagation: frA > frB > frC.

diffstat:

 sys/arch/powerpc/fpu/fpu_add.c |  12 +++++++-----
 sys/arch/powerpc/fpu/fpu_div.c |   7 ++++---
 sys/arch/powerpc/fpu/fpu_mul.c |  14 ++++++++------
 3 files changed, 19 insertions(+), 14 deletions(-)

diffs (106 lines):

diff -r 7186c0a74269 -r 8912bb16b831 sys/arch/powerpc/fpu/fpu_add.c
--- a/sys/arch/powerpc/fpu/fpu_add.c    Tue Sep 06 23:02:36 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_add.c    Tue Sep 06 23:04:08 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_add.c,v 1.6 2022/09/01 06:10:58 rin Exp $ */
+/*     $NetBSD: fpu_add.c,v 1.7 2022/09/06 23:04:08 rin Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -47,7 +47,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_add.c,v 1.6 2022/09/01 06:10:58 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_add.c,v 1.7 2022/09/06 23:04:08 rin Exp $");
 
 #include <sys/types.h>
 #if defined(DIAGNOSTIC)||defined(DEBUG)
@@ -93,13 +93,15 @@
        DUMPFPN(FPE_REG, x);
        DUMPFPN(FPE_REG, y);
        DPRINTF(FPE_REG, ("=>\n"));
-       ORDER(x, y);
-       if (ISNAN(y)) {
-               if (ISSNAN(y))
+       if (ISNAN(x) || ISNAN(y)) {
+               if (ISSNAN(x) || ISSNAN(y))
                        fe->fe_cx |= FPSCR_VXSNAN;
+               if (ISNAN(x))
+                       y = x;
                DUMPFPN(FPE_REG, y);
                return (y);
        }
+       ORDER(x, y);
        if (ISINF(y)) {
                if (ISINF(x) && x->fp_sign != y->fp_sign) {
                        fe->fe_cx |= FPSCR_VXISI;
diff -r 7186c0a74269 -r 8912bb16b831 sys/arch/powerpc/fpu/fpu_div.c
--- a/sys/arch/powerpc/fpu/fpu_div.c    Tue Sep 06 23:02:36 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_div.c    Tue Sep 06 23:04:08 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_div.c,v 1.8 2022/09/04 13:32:14 rin Exp $ */
+/*     $NetBSD: fpu_div.c,v 1.9 2022/09/06 23:04:08 rin Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -45,7 +45,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_div.c,v 1.8 2022/09/04 13:32:14 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_div.c,v 1.9 2022/09/06 23:04:08 rin Exp $");
 
 #include <sys/types.h>
 #if defined(DIAGNOSTIC)||defined(DEBUG)
@@ -182,9 +182,10 @@
        DUMPFPN(FPE_REG, y);
        DPRINTF(FPE_REG, ("=>\n"));
        if (ISNAN(x) || ISNAN(y)) {
-               ORDER(x, y);
                if (ISSNAN(x) || ISSNAN(y))
                        fe->fe_cx |= FPSCR_VXSNAN;
+               if (ISNAN(x))
+                       y = x;
                DUMPFPN(FPE_REG, y);
                return (y);
        }
diff -r 7186c0a74269 -r 8912bb16b831 sys/arch/powerpc/fpu/fpu_mul.c
--- a/sys/arch/powerpc/fpu/fpu_mul.c    Tue Sep 06 23:02:36 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_mul.c    Tue Sep 06 23:04:08 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_mul.c,v 1.6 2022/09/01 06:10:58 rin Exp $ */
+/*     $NetBSD: fpu_mul.c,v 1.7 2022/09/06 23:04:08 rin Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -45,7 +45,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_mul.c,v 1.6 2022/09/01 06:10:58 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_mul.c,v 1.7 2022/09/06 23:04:08 rin Exp $");
 
 #include <sys/types.h>
 #if defined(DIAGNOSTIC)||defined(DEBUG)
@@ -131,14 +131,16 @@
        DUMPFPN(FPE_REG, y);
        DPRINTF(FPE_REG, ("=>\n"));
 
-       ORDER(x, y);
-       if (ISNAN(y)) {
+       if (ISNAN(x) || ISNAN(y)) {
+               if (ISSNAN(x) || ISSNAN(y))
+                       fe->fe_cx |= FPSCR_VXSNAN;
+               if (ISNAN(x))
+                       SWAP(x, y);
                y->fp_sign ^= x->fp_sign;
-               if (ISSNAN(y))
-                       fe->fe_cx |= FPSCR_VXSNAN;
                DUMPFPN(FPE_REG, y);
                return (y);
        }
+       ORDER(x, y);
        if (ISINF(y)) {
                if (ISZERO(x)) {
                        fe->fe_cx |= FPSCR_VXIMZ;