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[src/trunk]: src/usr.sbin/cpuctl/arch macroify. NFC.
details: https://anonhg.NetBSD.org/src/rev/0350571df72f
branches: trunk
changeset: 359439:0350571df72f
user: ryo <ryo%NetBSD.org@localhost>
date: Thu Jan 06 08:46:43 2022 +0000
description:
macroify. NFC.
diffstat:
usr.sbin/cpuctl/arch/aarch64.c | 261 +++++++++++++++-------------------------
1 files changed, 100 insertions(+), 161 deletions(-)
diffs (truncated from 741 to 300 lines):
diff -r ec5a4f8c7f7b -r 0350571df72f usr.sbin/cpuctl/arch/aarch64.c
--- a/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 06 07:39:10 2022 +0000
+++ b/usr.sbin/cpuctl/arch/aarch64.c Thu Jan 06 08:46:43 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64.c,v 1.16 2022/01/05 19:53:32 ryo Exp $ */
+/* $NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.16 2022/01/05 19:53:32 ryo Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.17 2022/01/06 08:46:43 ryo Exp $");
#endif /* no lint */
#include <sys/types.h>
@@ -111,119 +111,114 @@
{ CPU_ID_INTEL, "Intel Corporation" }
};
+#define FIELDNAME(_bitpos, _bitwidth, _name) \
+ .bitpos = _bitpos, \
+ .bitwidth = _bitwidth, \
+ .name = _name
+
+#define FIELDINFO(_bitpos, _bitwidth, _name) \
+ FIELDNAME(_bitpos, _bitwidth, _name), \
+ .info = (const char *[1 << _bitwidth])
+
+
/* ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0 */
struct fieldinfo id_aa64pfr0_fieldinfo[] = {
{
- .bitpos = 0, .bitwidth = 4, .name = "EL0",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(0, 4, "EL0") {
[0] = "No EL0",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 4, .bitwidth = 4, .name = "EL1",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(4, 4, "EL1") {
[0] = "No EL1",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 8, .bitwidth = 4, .name = "EL2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(8, 4, "EL2") {
[0] = "No EL2",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 12, .bitwidth = 4, .name = "EL3",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(12, 4, "EL3") {
[0] = "No EL3",
[1] = "AArch64",
[2] = "AArch64/AArch32"
}
},
{
- .bitpos = 16, .bitwidth = 4, .name = "FP",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(16, 4, "FP") {
[0] = "Floating Point",
[1] = "Floating Point including half-precision support",
[15] = "No Floating Point"
}
},
{
- .bitpos = 20, .bitwidth = 4, .name = "AdvSIMD",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(20, 4, "AdvSIMD") {
[0] = "Advanced SIMD",
[1] = "Advanced SIMD including half-precision support",
[15] = "No Advanced SIMD"
}
},
{
- .bitpos = 24, .bitwidth = 4, .name = "GIC",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(24, 4, "GIC") {
[0] = "GIC CPU interface sysregs not implemented",
[1] = "GIC CPU interface sysregs v3.0/4.0 supported",
[3] = "GIC CPU interface sysregs v4.1 supported"
}
},
{
- .bitpos = 28, .bitwidth = 4, .name = "RAS",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(28, 4, "RAS") {
[0] = "Reliability/Availability/Serviceability not supported",
[1] = "Reliability/Availability/Serviceability supported",
[2] = "Reliability/Availability/Serviceability ARMv8.4 supported",
},
},
{
- .bitpos = 32, .bitwidth = 4, .name = "SVE",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(32, 4, "SVE") {
[0] = "Scalable Vector Extensions not implemented",
[1] = "Scalable Vector Extensions implemented",
},
},
{
- .bitpos = 36, .bitwidth = 4, .name = "SEL2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(36, 4, "SEL2") {
[0] = "Secure EL2 not implemented",
[1] = "Secure EL2 implemented",
},
},
{
- .bitpos = 40, .bitwidth = 4, .name = "MPAM",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(40, 4, "MPAM") {
[0] = "Memory Partitioning and Monitoring not implemented",
[1] = "Memory Partitioning and Monitoring implemented",
},
},
{
- .bitpos = 44, .bitwidth = 4, .name = "AMU",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(44, 4, "AMU") {
[0] = "Activity Monitors Extension not implemented",
[1] = "Activity Monitors Extension v1 ARMv8.4",
[2] = "Activity Monitors Extension v1 ARMv8.6",
},
},
{
- .bitpos = 48, .bitwidth = 4, .name = "DIT",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(48, 4, "DIT") {
[0] = "No Data-Independent Timing guarantees",
[1] = "Data-Independent Timing guaranteed by PSTATE.DIT",
},
},
{
- .bitpos = 56, .bitwidth = 4, .name = "CSV2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(56, 4, "CSV2") {
[0] = "Branch prediction might be Spectred",
[1] = "Branch prediction maybe not Spectred",
[2] = "Branch prediction probably not Spectred",
},
},
{
- .bitpos = 60, .bitwidth = 4, .name = "CSV3",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(60, 4, "CSV3") {
[0] = "Faults might be Spectred",
[1] = "Faults maybe not Spectred",
[2] = "Faults probably not Spectred",
@@ -235,31 +230,27 @@
/* ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 */
struct fieldinfo id_aa64pfr1_fieldinfo[] = {
{
- .bitpos = 0, .bitwidth = 4, .name = "BT",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(0, 4, "BT") {
[0] = "Branch Target Identification not implemented",
[1] = "Branch Target Identification implemented",
}
},
{
- .bitpos = 4, .bitwidth = 4, .name = "SSBS",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(4, 4, "SSBS") {
[0] = "Speculative Store Bypassing control not implemented",
[1] = "Speculative Store Bypassing control implemented",
[2] = "Speculative Store Bypassing control implemented, plus MSR/MRS"
}
},
{
- .bitpos = 8, .bitwidth = 4, .name = "MTE",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(8, 4, "MTE") {
[0] = "Tagged Memory Extension not implemented",
[1] = "Tagged Memory Extension implemented, EL0 only",
[2] = "Tagged Memory Extension implemented"
}
},
{
- .bitpos = 12, .bitwidth = 4, .name = "RAS_frac",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(12, 4, "RAS_frac") {
[0] = "Regular RAS",
[1] = "RAS plus registers",
}
@@ -270,97 +261,84 @@
/* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
struct fieldinfo id_aa64isar0_fieldinfo[] = {
{
- .bitpos = 4, .bitwidth = 4, .name = "AES",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(4, 4, "AES") {
[0] = "No AES",
[1] = "AESE/AESD/AESMC/AESIMC",
[2] = "AESE/AESD/AESMC/AESIMC+PMULL/PMULL2"
}
},
{
- .bitpos = 8, .bitwidth = 4, .name = "SHA1",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(8, 4, "SHA1") {
[0] = "No SHA1",
[1] = "SHA1C/SHA1P/SHA1M/SHA1H/SHA1SU0/SHA1SU1"
}
},
{
- .bitpos = 12, .bitwidth = 4, .name = "SHA2",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(12, 4, "SHA2") {
[0] = "No SHA2",
[1] = "SHA256H/SHA256H2/SHA256SU0/SHA256U1"
}
},
{
- .bitpos = 16, .bitwidth = 4, .name = "CRC32",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(16, 4, "CRC32") {
[0] = "No CRC32",
[1] = "CRC32B/CRC32H/CRC32W/CRC32X"
"/CRC32CB/CRC32CH/CRC32CW/CRC32CX"
}
},
{
- .bitpos = 20, .bitwidth = 4, .name = "Atomic",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(20, 4, "Atomic") {
[0] = "No Atomic",
[2] = "LDADD/LDCLR/LDEOR/LDSET/LDSMAX/LDSMIN"
"/LDUMAX/LDUMIN/CAS/CASP/SWP",
}
},
{
- .bitpos = 28, .bitwidth = 4, .name = "RDM",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(28, 4, "RDM") {
[0] = "No RDMA",
[1] = "SQRDMLAH/SQRDMLSH",
}
},
{
- .bitpos = 32, .bitwidth = 4, .name = "SHA3",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(32, 4, "SHA3") {
[0] = "No SHA3",
[1] = "EOR3/RAX1/XAR/BCAX",
}
},
{
- .bitpos = 36, .bitwidth = 4, .name = "SM3",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(36, 4, "SM3") {
[0] = "No SM3",
[1] = "SM3SS1/SM3TT1A/SM3TT1B/SM3TT2A/SM3TT2B"
"/SM3PARTW1/SM3PARTW2",
}
},
{
- .bitpos = 40, .bitwidth = 4, .name = "SM4",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(40, 4, "SM4") {
[0] = "No SM4",
[1] = "SM4E/SM4EKEY",
}
},
{
- .bitpos = 44, .bitwidth = 4, .name = "DP",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(44, 4, "DP") {
[0] = "No Dot Product",
[1] = "UDOT/SDOT",
}
},
{
- .bitpos = 48, .bitwidth = 4, .name = "FHM",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(48, 4, "FHM") {
[0] = "No FHM",
[1] = "FMLAL/FMLSL",
}
},
{
- .bitpos = 52, .bitwidth = 4, .name = "TS",
- .info = (const char *[16]) { /* 16=4bit */
+ FIELDINFO(52, 4, "TS") {
[0] = "No TS",
[1] = "CFINV/RMIF/SETF16/SETF8",
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