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[src/trunk]: src/sys/arch/mips/cavium/dev Remove unused snprintb format strings.



details:   https://anonhg.NetBSD.org/src/rev/ad1c6ea804b6
branches:  trunk
changeset: 1011184:ad1c6ea804b6
user:      simonb <simonb%NetBSD.org@localhost>
date:      Mon Jun 22 03:05:07 2020 +0000

description:
Remove unused snprintb format strings.

diffstat:

 sys/arch/mips/cavium/dev/octeon_asxreg.h     |  112 +------
 sys/arch/mips/cavium/dev/octeon_bootbusreg.h |   76 +----
 sys/arch/mips/cavium/dev/octeon_ciureg.h     |  250 +--------------
 sys/arch/mips/cavium/dev/octeon_corereg.h    |   64 +---
 sys/arch/mips/cavium/dev/octeon_fpareg.h     |  127 +-------
 sys/arch/mips/cavium/dev/octeon_gmxreg.h     |  449 +--------------------------
 sys/arch/mips/cavium/dev/octeon_gpioreg.h    |   15 +-
 sys/arch/mips/cavium/dev/octeon_ipdreg.h     |  303 +------------------
 sys/arch/mips/cavium/dev/octeon_mpireg.h     |   36 +--
 sys/arch/mips/cavium/dev/octeon_pip.c        |   49 +--
 sys/arch/mips/cavium/dev/octeon_pipreg.h     |  282 +---------------
 sys/arch/mips/cavium/dev/octeon_powreg.h     |  277 +----------------
 sys/arch/mips/cavium/dev/octeon_rnmreg.h     |   22 +-
 sys/arch/mips/cavium/dev/octeon_twsireg.h    |   52 +---
 sys/arch/mips/cavium/dev/octeon_usbcreg.h    |  340 +--------------------
 sys/arch/mips/cavium/dev/octeon_usbnreg.h    |  139 +--------
 16 files changed, 39 insertions(+), 2554 deletions(-)

diffs (truncated from 3162 to 300 lines):

diff -r c53b88aee320 -r ad1c6ea804b6 sys/arch/mips/cavium/dev/octeon_asxreg.h
--- a/sys/arch/mips/cavium/dev/octeon_asxreg.h  Mon Jun 22 02:51:06 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_asxreg.h  Mon Jun 22 03:05:07 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_asxreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/*     $NetBSD: octeon_asxreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
 
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -155,114 +155,4 @@
 #define ASX0_GMII_RX_DAT_SET_63_5              0xffffffe0
 #define ASX0_GMII_RX_DAT_SET_SETTING           0x0000001f
 
-/* ---- */
-
-#define        ASX0_RX_PRT_EN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x03\x3d"     "63_3\0" \
-       "f\x00\x03"     "PRT_EN\0"
-#define        ASX0_TX_PRT_EN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x03\x3d"     "63_3\0" \
-       "f\x00\x03"     "PRT_EN\0"
-#define        ASX0_INT_REG_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x0b\x35"     "63_11\0" \
-       "f\x08\x03"     "TXPSH\0" \
-       "b\x07"         "7\0" \
-       "f\x04\x03"     "TXPOP\0" \
-       "b\x03"         "3\0" \
-       "f\x00\x03"     "OVRFLW\0"
-#define        ASX0_INT_EN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x0b\x35"     "63_11\0" \
-       "f\x08\x03"     "TXPSH\0" \
-       "b\x07"         "7\0" \
-       "f\x04\x03"     "TXPOP\0" \
-       "b\x03"         "3\0" \
-       "f\x00\x03"     "OVRFLW\0"
-#define        ASX0_RX_CLK_SET0_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_RX_CLK_SET1_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_RX_CLK_SET2_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_PRT_LOOP_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x07\x39"     "63_7\0" \
-       "f\x04\x03"     "EXT_LOOP\0" \
-       "b\x03"         "3\0" \
-       "f\x00\x03"     "PRT_LOOP\0"
-#define        ASX0_TX_CLK_SET0_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_TX_CLK_SET1_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_TX_CLK_SET2_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_COMP_BYP_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_TX_HI_WATER000_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_TX_HI_WATER001_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_TX_HI_WATER002_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-#define        ASX0_GMII_RX_CLK_SET_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x05\x3b"     "63_5\0" \
-       "f\x00\x05"     "SETTING\0"
-#define        ASX0_GMII_RX_DAT_SET_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x05\x3b"     "63_5\0" \
-       "f\x00\x05"     "SETTING\0"
-#define        ASX0_MII_RX_DAT_SET_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-
-
 #endif /* _OCTEON_ASXREG_H_ */
diff -r c53b88aee320 -r ad1c6ea804b6 sys/arch/mips/cavium/dev/octeon_bootbusreg.h
--- a/sys/arch/mips/cavium/dev/octeon_bootbusreg.h      Mon Jun 22 02:51:06 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_bootbusreg.h      Mon Jun 22 03:05:07 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_bootbusreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $     */
+/*     $NetBSD: octeon_bootbusreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $     */
 
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -116,21 +116,6 @@
 #define        MIO_BOOT_BIST_STAT_LOC                  UINT64_C(0x0000000000000002)
 #define        MIO_BOOT_BIST_STAT_NCBI                 UINT64_C(0x0000000000000001)
 
-/* ---- snprintb */
-
-#define        MIO_BOOT_REG_CFGN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x24"         "SAM\0" \
-       "f\x22\x02"     "WE_EXT\0" \
-       "f\x20\x02"     "OE_EXT\0" \
-       "b\x1f"         "EN\0" \
-       "b\x1e"         "OR\0" \
-       "b\x1d"         "ALE\0" \
-       "b\x1c"         "WIDTH\0" \
-       "f\x10\x0c"     "SIZE\0" \
-       "f\x00\x10"     "BASE\0"
 #define        MIO_BOOT_REG_CFG0_BITS                  MIO_BOOT_REG_CFGN_BITS
 #define        MIO_BOOT_REG_CFG1_BITS                  MIO_BOOT_REG_CFGN_BITS
 #define        MIO_BOOT_REG_CFG2_BITS                  MIO_BOOT_REG_CFGN_BITS
@@ -140,23 +125,6 @@
 #define        MIO_BOOT_REG_CFG6_BITS                  MIO_BOOT_REG_CFGN_BITS
 #define        MIO_BOOT_REG_CFG7_BITS                  MIO_BOOT_REG_CFGN_BITS
 
-#define        MIO_BOOT_REG_TIMN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x3f"         "PAGEM\0" \
-       "b\x3e"         "WAITM\0" \
-       "f\x3c\x02"     "PAGES\0" \
-       "f\x36\x06"     "ALE\0" \
-       "f\x30\x06"     "PAGE\0" \
-       "f\x2a\x06"     "WAIT\0" \
-       "f\x24\x06"     "PAUSE\0" \
-       "f\x1e\x06"     "WR_HLD\0" \
-       "f\x18\x06"     "RD_HLD\0" \
-       "f\x12\x06"     "WE\0" \
-       "f\x0c\x06"     "OE\0" \
-       "f\x06\x06"     "CE\0" \
-       "f\x00\x06"     "ADR\0"
 #define        MIO_BOOT_REG_TIM0_BITS                  MIO_BOOT_REG_TIMN_BITS
 #define        MIO_BOOT_REG_TIM1_BITS                  MIO_BOOT_REG_TIMN_BITS
 #define        MIO_BOOT_REG_TIM2_BITS                  MIO_BOOT_REG_TIMN_BITS
@@ -166,12 +134,6 @@
 #define        MIO_BOOT_REG_TIM6_BITS                  MIO_BOOT_REG_TIMN_BITS
 #define        MIO_BOOT_REG_TIM7_BITS                  MIO_BOOT_REG_TIMN_BITS
 
-#define        MIO_BOOT_LOC_CFGN_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x1f"         "EN\0" \
-       "f\x03\x19"     "BASE\0"
 #define        MIO_BOOT_LOC_CFG0_BITS                  MIO_BOOT_LOC_CFGN_BITS
 #define        MIO_BOOT_LOC_CFG1_BITS                  MIO_BOOT_LOC_CFGN_BITS
 #define        MIO_BOOT_LOC_CFG2_BITS                  MIO_BOOT_LOC_CFGN_BITS
@@ -181,42 +143,6 @@
 #define        MIO_BOOT_LOC_CFG6_BITS                  MIO_BOOT_LOC_CFGN_BITS
 #define        MIO_BOOT_LOC_CFG7_BITS                  MIO_BOOT_LOC_CFGN_BITS
 
-#define        MIO_BOOT_LOC_ADR_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x03\x05"     "ADR\0"
-
-#define        MIO_BOOT_ERR_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x01"         "WAIT_ERR\0" \
-       "b\x00"         "ADR_ERR\0"
-
-#define        MIO_BOOT_INT_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x01"         "WAIT_INT\0" \
-       "b\x00"         "ADR_INT\0"
-
-#define        MIO_BOOT_THR_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "f\x08\x06"     "FIF_CNT\0" \
-       "f\x00\x06"     "FIF_THR\0"
-
-#define        MIO_BOOT_BIST_STAT_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x03"         "NCBO_1\0" \
-       "b\x02"         "NCBO_0\0" \
-       "b\x01"         "LOC\0" \
-       "b\x00"         "NCBI\0"
-
 /* ---- bus_space */
 
 #define        MIO_BOOT_REG_CFG0_OFFSET                0x0000
diff -r c53b88aee320 -r ad1c6ea804b6 sys/arch/mips/cavium/dev/octeon_ciureg.h
--- a/sys/arch/mips/cavium/dev/octeon_ciureg.h  Mon Jun 22 02:51:06 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_ciureg.h  Mon Jun 22 03:05:07 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_ciureg.h,v 1.7 2020/06/19 02:23:43 simonb Exp $ */
+/*     $NetBSD: octeon_ciureg.h,v 1.8 2020/06/22 03:05:07 simonb Exp $ */
 
 /*
  * Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -263,290 +263,42 @@
 #define        CIU_PCI_INTA_XXX_63_2                   UINT64_C(0xfffffffffffffffc)
 #define        CIU_PCI_INTA_INT                        UINT64_C(0x0000000000000003)
 
-/* -- snprintb(9) */
-
-#define        CIU_INTX_SUM0_BITS \
-       "\177"          /* new format */ \
-       "\020"          /* hex display */ \
-       "\020"          /* %016x format */ \
-       "b\x3a"         "MPI\0" \
-       "b\x39"         "PCM\0" \
-       "b\x38"         "USB\0" \
-       "b\x37"         "TIMER_3\0" \
-       "b\x36"         "TIMER_2\0" \
-       "b\x35"         "TIMER_1\0" \
-       "b\x34"         "TIMER_0\0" \
-       "f\x34\x04"     "TIMER\0" \
-       "b\x32"         "IPD_DRP\0" \
-       "b\x30"         "GMX_DRP\0" \
-       "b\x2f"         "TRACE\0" \
-       "b\x2e"         "RML\0" \
-       "b\x2d"         "TWSI\0" \
-       "b\x2c"         "WDOG_SUM\0" \
-       "b\x2b"         "PCI_MSI_63_48\0" \
-       "b\x2a"         "PCI_MSI_47_32\0" \
-       "b\x29"         "PCI_MSI_31_16\0" \
-       "b\x28"         "PCI_MSI_15_0\0" \
-       "f\x28\x04"     "PCI_MSI\0" \
-       "b\x27"         "PCI_INT_D\0" \
-       "b\x26"         "PCI_INT_C\0" \
-       "b\x25"         "PCI_INT_B\0" \
-       "f\x24\x04"     "PCI_INT\0" \
-       "b\x24"         "PCI_INT_A\0" \
-       "b\x23"         "UART_1\0" \
-       "b\x22"         "UART_0\0" \
-       "f\x22\x02"     "UART\0" \
-       "b\x21"         "MBOX_31_16\0" \
-       "f\x20\x02"     "MBOX\0" \
-       "b\x20"         "MBOX_15_0\0" \
-       "b\x1f"         "GPIO_15\0" \
-       "b\x1e"         "GPIO_14\0" \
-       "b\x1d"         "GPIO_13\0" \
-       "b\x1c"         "GPIO_12\0" \
-       "b\x1b"         "GPIO_11\0" \
-       "b\x1a"         "GPIO_10\0" \
-       "b\x19"         "GPIO_9\0" \
-       "b\x18"         "GPIO_8\0" \
-       "b\x17"         "GPIO_7\0" \
-       "b\x16"         "GPIO_6\0" \
-       "b\x15"         "GPIO_5\0" \
-       "b\x14"         "GPIO_4\0" \
-       "b\x13"         "GPIO_3\0" \
-       "b\x12"         "GPIO_2\0" \
-       "b\x11"         "GPIO_1\0" \
-       "b\x10"         "GPIO_0\0" \



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