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[src/trunk]: src/usr.sbin/cpuctl/arch - AMD CPUID Fn8000_0001d Cache Topology...



details:   https://anonhg.NetBSD.org/src/rev/9e47abc711c3
branches:  trunk
changeset: 1000493:9e47abc711c3
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Jul 26 10:03:40 2019 +0000

description:
- AMD CPUID Fn8000_0001d Cache Topology Information leaf is almost the same as
  Intel Deterministic Cache Parameter Leaf(0x04), so make new
  cpu_dcp_cacheinfo() and share it.
- AMD's L2 and L3's cache descriptor's definition is the same, so use one
  common definition.
- KNF.

XXX Split some common functions to new identcpu_subr.c or use #ifdef _KERNEK
... #endif in identcpu.c to share from both kernel and cpuctl?

diffstat:

 sys/arch/x86/include/cacheinfo.h  |   21 +---
 sys/arch/x86/include/specialreg.h |   10 +-
 sys/arch/x86/x86/identcpu.c       |  174 ++++++++++++++++-----------------
 usr.sbin/cpuctl/arch/i386.c       |  193 ++++++++++++++++++-------------------
 4 files changed, 193 insertions(+), 205 deletions(-)

diffs (truncated from 692 to 300 lines):

diff -r 62fc0ec3cf44 -r 9e47abc711c3 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Fri Jul 26 09:26:56 2019 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Fri Jul 26 10:03:40 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.27 2019/07/24 10:45:47 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.28 2019/07/26 10:03:40 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -339,7 +339,7 @@
 __CI_TBL(0,               0,    0,               0,  0, NULL)  \
 }
 
-#define AMD_L2CACHE_INFO { \
+#define AMD_L2L3CACHE_INFO {        \
 __CI_TBL(0, 0x01,    1, 0, 0, NULL), \
 __CI_TBL(0, 0x02,    2, 0, 0, NULL), \
 __CI_TBL(0, 0x03,    3, 0, 0, NULL), \
@@ -347,22 +347,7 @@
 __CI_TBL(0, 0x05,    6, 0, 0, NULL), \
 __CI_TBL(0, 0x06,    8, 0, 0, NULL), \
 __CI_TBL(0, 0x08,   16, 0, 0, NULL), \
-__CI_TBL(0, 0x0a,   32, 0, 0, NULL), \
-__CI_TBL(0, 0x0b,   48, 0, 0, NULL), \
-__CI_TBL(0, 0x0c,   64, 0, 0, NULL), \
-__CI_TBL(0, 0x0d,   96, 0, 0, NULL), \
-__CI_TBL(0, 0x0e,  128, 0, 0, NULL), \
-__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
-__CI_TBL(0, 0x00,    0, 0, 0, NULL)  \
-}
-
-#define AMD_L3CACHE_INFO { \
-__CI_TBL(0, 0x01,    1, 0, 0, NULL), \
-__CI_TBL(0, 0x02,    2, 0, 0, NULL), \
-__CI_TBL(0, 0x04,    4, 0, 0, NULL), \
-__CI_TBL(0, 0x06,    8, 0, 0, NULL), \
-__CI_TBL(0, 0x08,   16, 0, 0, NULL), \
-__CI_TBL(0, 0x09,   16, 0, 0, NULL), \
+    /* 0x09:Use Fn8000_001D */      \
 __CI_TBL(0, 0x0a,   32, 0, 0, NULL), \
 __CI_TBL(0, 0x0b,   48, 0, 0, NULL), \
 __CI_TBL(0, 0x0c,   64, 0, 0, NULL), \
diff -r 62fc0ec3cf44 -r 9e47abc711c3 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Jul 26 09:26:56 2019 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Jul 26 10:03:40 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.149 2019/07/13 09:28:03 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.150 2019/07/26 10:03:40 msaitoh Exp $ */
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -736,6 +736,14 @@
        "\21" "VGIF"
 
 /*
+ * AMD Fn8000_0001d  Cache Topology Information.
+ * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04)
+ * except the following:
+ *     No Cores/package (%eax bit 31..26)
+ *     No Complex cache indexing (%edx bit 2)
+ */
+
+/*
  * Centaur Extended Feature flags
  */
 #define CPUID_VIA_HAS_RNG      0x00000004      /* Random number generator */
diff -r 62fc0ec3cf44 -r 9e47abc711c3 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Fri Jul 26 09:26:56 2019 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Fri Jul 26 10:03:40 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.92 2019/06/26 12:29:01 mgorny Exp $     */
+/*     $NetBSD: identcpu.c,v 1.93 2019/07/26 10:03:40 msaitoh Exp $    */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.92 2019/06/26 12:29:01 mgorny Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93 2019/07/26 10:03:40 msaitoh Exp $");
 
 #include "opt_xen.h"
 
@@ -62,11 +62,8 @@
 
 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO;
 
-static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 
-       AMD_L2CACHE_INFO;
-
-static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 
-       AMD_L3CACHE_INFO;
+static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 
+       AMD_L2L3CACHE_INFO;
 
 int cpu_vendor;
 char cpu_brand_string[49];
@@ -109,6 +106,66 @@
        return (NULL);
 }
 
+/*
+ * Get cache info from one of the following:
+ *     Intel Deterministic Cache Parameter Leaf (0x04)
+ *     AMD Cache Topology Information Leaf (0x8000001d)
+ */
+static void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+       u_int descs[4];
+       int type, level, ways, partitions, linesize, sets, totalsize;
+       int caitype = -1;
+       int i;
+
+       for (i = 0; ; i++) {
+               x86_cpuid2(leaf, i, descs);
+               type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+               if (type == CPUID_DCP_CACHETYPE_N)
+                       break;
+               level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+               switch (level) {
+               case 1:
+                       if (type == CPUID_DCP_CACHETYPE_I)
+                               caitype = CAI_ICACHE;
+                       else if (type == CPUID_DCP_CACHETYPE_D)
+                               caitype = CAI_DCACHE;
+                       else
+                               caitype = -1;
+                       break;
+               case 2:
+                       if (type == CPUID_DCP_CACHETYPE_U)
+                               caitype = CAI_L2CACHE;
+                       else
+                               caitype = -1;
+                       break;
+               case 3:
+                       if (type == CPUID_DCP_CACHETYPE_U)
+                               caitype = CAI_L3CACHE;
+                       else
+                               caitype = -1;
+                       break;
+               default:
+                       caitype = -1;
+                       break;
+               }
+               if (caitype == -1)
+                       continue;
+
+               ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
+               partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
+                   + 1;
+               linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
+                   + 1;
+               sets = descs[2] + 1;
+               totalsize = ways * partitions * linesize * sets;
+               ci->ci_cinfo[caitype].cai_totalsize = totalsize;
+               ci->ci_cinfo[caitype].cai_associativity = ways;
+               ci->ci_cinfo[caitype].cai_linesize = linesize;
+       }
+}
+
 static void
 cpu_probe_intel_cache(struct cpu_info *ci)
 {
@@ -142,59 +199,11 @@
                }
        }
 
-       if (cpuid_level >= 4) {
-               int type, level;
-               int ways, partitions, linesize, sets;
-               int caitype = -1;
-               int totalsize;
+       if (cpuid_level < 4)
+               return;
 
-               /* Parse the cache info from `cpuid leaf 4', if we have it. */
-               for (i = 0; ; i++) {
-                       x86_cpuid2(4, i, descs);
-                       type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
-                       if (type == CPUID_DCP_CACHETYPE_N)
-                               break;
-                       level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
-                       switch (level) {
-                       case 1:
-                               if (type == CPUID_DCP_CACHETYPE_I)
-                                       caitype = CAI_ICACHE;
-                               else if (type == CPUID_DCP_CACHETYPE_D)
-                                       caitype = CAI_DCACHE;
-                               else
-                                       caitype = -1;
-                               break;
-                       case 2:
-                               if (type == CPUID_DCP_CACHETYPE_U)
-                                       caitype = CAI_L2CACHE;
-                               else
-                                       caitype = -1;
-                               break;
-                       case 3:
-                               if (type == CPUID_DCP_CACHETYPE_U)
-                                       caitype = CAI_L3CACHE;
-                               else
-                                       caitype = -1;
-                               break;
-                       default:
-                               caitype = -1;
-                               break;
-                       }
-                       if (caitype == -1)
-                               continue;
-
-                       ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
-                       partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
-                           + 1;
-                       linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
-                           + 1;
-                       sets = descs[2] + 1;
-                       totalsize = ways * partitions * linesize * sets;
-                       ci->ci_cinfo[caitype].cai_totalsize = totalsize;
-                       ci->ci_cinfo[caitype].cai_associativity = ways;
-                       ci->ci_cinfo[caitype].cai_linesize = linesize;
-               }
-       }
+       /* Parse the cache info from `cpuid leaf 4', if we have it. */
+       cpu_dcp_cacheinfo(ci, 4);
 }
 
 static void
@@ -238,31 +247,21 @@
        family = CPUID_TO_FAMILY(ci->ci_signature);
        model = CPUID_TO_MODEL(ci->ci_signature);
 
-       /*
-        * K5 model 0 has none of this info.
-        */
+       /* K5 model 0 has none of this info. */
        if (family == 5 && model == 0)
                return;
 
-       /*
-        * Determine the largest extended function value.
-        */
+       /* Determine the largest extended function value. */
        x86_cpuid(0x80000000, descs);
        lfunc = descs[0];
 
-       /*
-        * Determine L1 cache/TLB info.
-        */
-       if (lfunc < 0x80000005) {
-               /* No L1 cache info available. */
+       if (lfunc < 0x80000005)
                return;
-       }
 
+       /* Determine L1 cache/TLB info. */
        x86_cpuid(0x80000005, descs);
 
-       /*
-        * K6-III and higher have large page TLBs.
-        */
+       /* K6-III and higher have large page TLBs. */
        if ((family == 5 && model >= 9) || family >= 6) {
                cai = &ci->ci_cinfo[CAI_ITLB2];
                cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
@@ -295,14 +294,10 @@
        cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]);
        cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]);
 
-       /*
-        * Determine L2 cache/TLB info.
-        */
-       if (lfunc < 0x80000006) {
-               /* No L2 cache info available. */
+       if (lfunc < 0x80000006)
                return;
-       }
 
+       /* Determine L2 cache/TLB info. */
        x86_cpuid(0x80000006, descs);
 
        cai = &ci->ci_cinfo[CAI_L2CACHE];
@@ -310,35 +305,33 @@
        cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
        cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
 
-       cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+       cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
            cai->cai_associativity);
        if (cp != NULL)
                cai->cai_associativity = cp->cai_associativity;
        else
                cai->cai_associativity = 0;     /* XXX Unknown/reserved */
 
-       if (family < 0xf) {
-               /* No L3 cache info available. */
+       if (family < 0xf)
                return;
-       }



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