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[src/trunk]: src/sys/arch/x86 No functional change:



details:   https://anonhg.NetBSD.org/src/rev/5096e6038f0a
branches:  trunk
changeset: 999676:5096e6038f0a
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Jun 14 05:59:39 2019 +0000

description:
No functional change:
- Rename macros:
  - ICR, LVT and MSIDATA can share the bit definitions. Remove redundant
    definitions and use the common macros.
  - Consistently use LAPIC_LVT_ for all local vector table's macro names.
- Use __BITS().
- Add definition for TSC-deadline (LAPIC_LVT_TMM_TSCDLT).

diffstat:

 sys/arch/x86/include/i82489reg.h |  110 +++++++++++++++-----------------------
 sys/arch/x86/pci/msipic.c        |   12 ++--
 sys/arch/x86/x86/lapic.c         |   63 ++++++++++++---------
 3 files changed, 85 insertions(+), 100 deletions(-)

diffs (truncated from 354 to 300 lines):

diff -r 0f15ae2d3fb2 -r 5096e6038f0a sys/arch/x86/include/i82489reg.h
--- a/sys/arch/x86/include/i82489reg.h  Fri Jun 14 04:48:34 2019 +0000
+++ b/sys/arch/x86/include/i82489reg.h  Fri Jun 14 05:59:39 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i82489reg.h,v 1.18 2019/06/13 15:10:27 msaitoh Exp $   */
+/*     $NetBSD: i82489reg.h,v 1.19 2019/06/14 05:59:39 msaitoh Exp $   */
 
 /*-
  * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -79,63 +79,60 @@
 #define LAPIC_IRR      0x200   /* Interrupt Req RO */
 #define LAPIC_ESR      0x280   /* Err status. RW */
 
-#define LAPIC_LVT_CMCI 0x2f0   /* Loc.vec (CMCI) RW */
+/* Common definitions for ICR, LVT and MSIDATA */
+#define LAPIC_VECTOR_MASK    __BITS(7, 0)
+#define LAPIC_DLMODE_MASK    __BITS(10, 8)     /* Delivery Mode */
+#define LAPIC_DLMODE_FIXED   __SHIFTIN(0, LAPIC_DLMODE_MASK)
+#define LAPIC_DLMODE_LOW     __SHIFTIN(1, LAPIC_DLMODE_MASK) /* NA in x2APIC */
+#define LAPIC_DLMODE_SMI     __SHIFTIN(2, LAPIC_DLMODE_MASK)
+#define LAPIC_DLMODE_NMI     __SHIFTIN(4, LAPIC_DLMODE_MASK)
+#define LAPIC_DLMODE_INIT    __SHIFTIN(5, LAPIC_DLMODE_MASK)
+#define LAPIC_DLMODE_STARTUP __SHIFTIN(6, LAPIC_DLMODE_MASK) /* NA in LVT,MSI*/
+#define LAPIC_DLMODE_EXTINT  __SHIFTIN(7, LAPIC_DLMODE_MASK) /* NA in x2APIC */
 
-#define LAPIC_ICRLO    0x300   /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
-#      define LAPIC_DLMODE_MASK        0x00000700      /* Delivery Mode */
-#      define LAPIC_DLMODE_FIXED       0x00000000
-#      define LAPIC_DLMODE_LOW         0x00000100      /* N/A in x2APIC mode */
-#      define LAPIC_DLMODE_SMI         0x00000200
-#      define LAPIC_DLMODE_NMI         0x00000400
-#      define LAPIC_DLMODE_INIT        0x00000500
-#      define LAPIC_DLMODE_STARTUP     0x00000600
-#      define LAPIC_DLMODE_EXTINT      0x00000700      /* N/A in x2APIC mode */
+#define LAPIC_DLSTAT_BUSY    __BIT(12) /* NA in x2APIC nor MSI */
+#define LAPIC_DLSTAT_IDLE    0x00000000
 
-#      define LAPIC_DSTMODE_PHYS       0x00000000
-#      define LAPIC_DSTMODE_LOG        0x00000800
+#define LAPIC_LEVEL_MASK     __BIT(14) /* LAPIC_LVT_LINT_RIRR in LVT LINT */
+#define LAPIC_LEVEL_ASSERT   LAPIC_LEVEL_MASK
+#define LAPIC_LEVEL_DEASSERT 0x00000000
 
-#      define LAPIC_DLSTAT_BUSY        0x00001000      /* N/A in x2APIC mode */
-#      define LAPIC_DLSTAT_IDLE        0x00000000      /* N/A in x2APIC mode */
+#define LAPIC_TRIGMODE_MASK   __BIT(15)
+#define LAPIC_TRIGMODE_EDGE   0x00000000
+#define LAPIC_TRIGMODE_LEVEL  LAPIC_TRIGMODE_MASK
 
-#      define LAPIC_LEVEL_MASK         0x00004000
-#      define LAPIC_LEVEL_ASSERT       0x00004000
-#      define LAPIC_LEVEL_DEASSERT     0x00000000
+/* Common definitions for LVT */
+#define LAPIC_LVT_MASKED     __BIT(16)
+
+#define LAPIC_LVT_CMCI 0x2f0   /* Loc.vec (CMCI) RW */
+#define LAPIC_ICRLO    0x300   /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
 
-#      define LAPIC_TRIGGER_MASK       0x00008000
-#      define LAPIC_TRIGGER_EDGE       0x00000000
-#      define LAPIC_TRIGGER_LEVEL      0x00008000
+#      define LAPIC_DSTMODE_MASK       __BIT(11)
+#      define LAPIC_DSTMODE_PHYS       __SHIFTIN(0, LAPIC_DSTMODE_MASK)
+#      define LAPIC_DSTMODE_LOG        __SHIFTIN(1, LAPIC_DSTMODE_MASK)
 
-#      define LAPIC_DEST_MASK          0x000c0000
-#      define LAPIC_DEST_DEFAULT       0x00000000
-#      define LAPIC_DEST_SELF          0x00040000
-#      define LAPIC_DEST_ALLINCL       0x00080000
-#      define LAPIC_DEST_ALLEXCL       0x000c0000
+#      define LAPIC_DEST_MASK          __BITS(19, 18)
+#      define LAPIC_DEST_DEFAULT       __SHIFTIN(0, LAPIC_DEST_MASK)
+#      define LAPIC_DEST_SELF          __SHIFTIN(1, LAPIC_DEST_MASK)
+#      define LAPIC_DEST_ALLINCL       __SHIFTIN(2, LAPIC_DEST_MASK)
+#      define LAPIC_DEST_ALLEXCL       __SHIFTIN(3, LAPIC_DEST_MASK)
 
 #define LAPIC_ICRHI    0x310   /* Int. cmd. (xAPIC: RW, x2APIC: NA) */
 
-#define LAPIC_LVTT     0x320   /* Loc.vec.(timer) RW */
-#      define LAPIC_LVTT_VEC_MASK      0x000000ff
-#      define LAPIC_LVTT_DS            0x00001000
-#      define LAPIC_LVTT_M             0x00010000
-#      define LAPIC_LVTT_TM            0x00020000
+#define LAPIC_LVT_TIMER        0x320   /* Loc.vec.(timer) RW */
+#      define LAPIC_LVT_TMM            __BITS(18, 17)
+#      define LAPIC_LVT_TMM_ONESHOT    __SHIFTIN(0, LAPIC_LVT_TMM)
+#      define LAPIC_LVT_TMM_PERIODIC   __SHIFTIN(1, LAPIC_LVT_TMM)
+#      define LAPIC_LVT_TMM_TSCDLT     __SHIFTIN(2, LAPIC_LVT_TMM)
 
-#define LAPIC_TMINT    0x330   /* Loc.vec (Thermal) RW */
-#define LAPIC_PCINT    0x340   /* Loc.vec (Perf Mon) RW */
-#define LAPIC_LVINT0   0x350   /* Loc.vec (LINT0) RW */
-#      define LAPIC_LVT_DM_MASK        0x00000700
-#      define LAPIC_LVT_DM_FIXED       0x00000000
-#      define LAPIC_LVT_DM_SMI         0x00000200
-#      define LAPIC_LVT_DM_NMI         0x00000400
-#      define LAPIC_LVT_DM_INIT        0x00000500
-#      define LAPIC_LVT_DM_EXTINT      0x00000700
-#      define LAPIC_LVT_MASKED         0x00010000
-#      define LAPIC_LVT_LEVTRIG        0x00008000
-#      define LAPIC_LVT_REMOTE_IRR     0x00004000
-#      define LAPIC_INP_POL            0x00002000
-#      define LAPIC_PEND_SEND          0x00001000
+#define LAPIC_LVT_THERM        0x330   /* Loc.vec (Thermal) RW */
+#define LAPIC_LVT_PCINT        0x340   /* Loc.vec (Perf Mon) RW */
+#define LAPIC_LVT_LINT0        0x350   /* Loc.vec (LINT0) RW */
+#      define LAPIC_LVT_LINT_INP_POL   __BIT(13)
+#      define LAPIC_LVT_LINT_RIRR      __BIT(14)
 
-#define LAPIC_LVINT1   0x360   /* Loc.vec (LINT1) RW */
-#define LAPIC_LVERR    0x370   /* Loc.vec (ERROR) RW */
+#define LAPIC_LVT_LINT1        0x360   /* Loc.vec (LINT1) RW */
+#define LAPIC_LVT_ERR  0x370   /* Loc.vec (ERROR) RW */
 #define LAPIC_ICR_TIMER        0x380   /* Initial count RW */
 #define LAPIC_CCR_TIMER        0x390   /* Current count RO */
 
@@ -159,25 +156,6 @@
 #define        LAPIC_MSIADDR_DM                __BIT(2)
 #define        LAPIC_MSIADDR_RSVD1_MASK        __BITS(1, 0)
 
-#define        LAPIC_MSIDATA_VECTOR_MASK       __BITS(7, 0)
-#define        LAPIC_MSIDATA_DM_MASK           __BITS(10, 8)
-#define        LAPIC_MSIDATA_DM_FIXED          __SHIFTIN(0, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_LOPRI          __SHIFTIN(1, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_SMI            __SHIFTIN(2, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_RSVD0          __SHIFTIN(3, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_NMI            __SHIFTIN(4, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_INIT           __SHIFTIN(5, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_RSVD1          __SHIFTIN(6, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_DM_EXTINT         __SHIFTIN(7, LAPIC_MSIDATA_DM_MASK)
-#define        LAPIC_MSIDATA_RSVD0_MASK        __BITS(13, 11)
-#define        LAPIC_MSIDATA_LEVEL_MASK        __BIT(14)
-#define        LAPIC_MSIDATA_LEVEL_DEASSERT    __SHIFTIN(0, LAPIC_MSIDATA_LEVEL_MASK)
-#define        LAPIC_MSIDATA_LEVEL_ASSERT      __SHIFTIN(1, LAPIC_MSIDATA_LEVEL_MASK)
-#define        LAPIC_MSIDATA_TRGMODE_MASK      __BIT(15)
-#define        LAPIC_MSIDATA_TRGMODE_EDGE      __SHIFTIN(0,LAPIC_MSIDATA_TRGMODE_MASK)
-#define        LAPIC_MSIDATA_TRGMODE_LEVEL     __SHIFTIN(1,LAPIC_MSIDATA_TRGMODE_MASK)
-#define        LAPIC_MSIDATA_RSVD1_MASK        __BITS(31, 16)
-
 #define LAPIC_BASE             0xfee00000
 
 #define LAPIC_IRQ_MASK(i)      (1 << ((i) + 1))
diff -r 0f15ae2d3fb2 -r 5096e6038f0a sys/arch/x86/pci/msipic.c
--- a/sys/arch/x86/pci/msipic.c Fri Jun 14 04:48:34 2019 +0000
+++ b/sys/arch/x86/pci/msipic.c Fri Jun 14 05:59:39 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: msipic.c,v 1.12 2019/04/01 06:20:40 msaitoh Exp $      */
+/*     $NetBSD: msipic.c,v 1.13 2019/06/14 05:59:40 msaitoh Exp $      */
 
 /*
  * Copyright (c) 2015 Internet Initiative Japan Inc.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.12 2019/04/01 06:20:40 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.13 2019/06/14 05:59:40 msaitoh Exp $");
 
 #include "opt_intrdebug.h"
 
@@ -384,8 +384,8 @@
        addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid,
            LAPIC_MSIADDR_DSTID_MASK);
        /* If trigger mode is edge, it don't care level for trigger mode. */
-       data = __SHIFTIN(idt_vec, LAPIC_MSIDATA_VECTOR_MASK)
-               | LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_DM_FIXED;
+       data = __SHIFTIN(idt_vec, LAPIC_VECTOR_MASK)
+               | LAPIC_TRIGMODE_EDGE | LAPIC_DLMODE_FIXED;
 
        ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
        if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -550,8 +550,8 @@
        addr = LAPIC_MSIADDR_BASE | __SHIFTIN(ci->ci_cpuid,
            LAPIC_MSIADDR_DSTID_MASK);
        /* If trigger mode is edge, it don't care level for trigger mode. */
-       data = __SHIFTIN(idt_vec, LAPIC_MSIDATA_VECTOR_MASK)
-               | LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_DM_FIXED;
+       data = __SHIFTIN(idt_vec, LAPIC_VECTOR_MASK)
+               | LAPIC_TRIGMODE_EDGE | LAPIC_DLMODE_FIXED;
 
        bstag = pic->pic_msipic->mp_bstag;
        bshandle = pic->pic_msipic->mp_bshandle;
diff -r 0f15ae2d3fb2 -r 5096e6038f0a sys/arch/x86/x86/lapic.c
--- a/sys/arch/x86/x86/lapic.c  Fri Jun 14 04:48:34 2019 +0000
+++ b/sys/arch/x86/x86/lapic.c  Fri Jun 14 05:59:39 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: lapic.c,v 1.73 2019/06/13 07:42:45 msaitoh Exp $       */
+/*     $NetBSD: lapic.c,v 1.74 2019/06/14 05:59:39 msaitoh Exp $       */
 
 /*-
  * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.73 2019/06/13 07:42:45 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.74 2019/06/14 05:59:39 msaitoh Exp $");
 
 #include "acpica.h"
 #include "ioapic.h"
@@ -423,9 +423,9 @@
 #ifdef MULTIPROCESSOR
        if (mp_verbose) {
                apic_format_redir(device_xname(ci->ci_dev), "prelint", 0, 0,
-                   lapic_readreg(LAPIC_LVINT0));
+                   lapic_readreg(LAPIC_LVT_LINT0));
                apic_format_redir(device_xname(ci->ci_dev), "prelint", 1, 0,
-                   lapic_readreg(LAPIC_LVINT1));
+                   lapic_readreg(LAPIC_LVT_LINT1));
        }
 #endif
 
@@ -434,18 +434,18 @@
         * the 8259A for interrupt delivery.  Otherwise request the LAPIC to
         * get external interrupts via LINT0 for the primary CPU.
         */
-       lint0 = LAPIC_LVT_DM_EXTINT;
+       lint0 = LAPIC_DLMODE_EXTINT;
        if (nioapics > 0 || !CPU_IS_PRIMARY(curcpu()))
                lint0 |= LAPIC_LVT_MASKED;
-       lapic_writereg(LAPIC_LVINT0, lint0);
+       lapic_writereg(LAPIC_LVT_LINT0, lint0);
 
        /*
         * Non Maskable Interrupts are to be delivered to the primary CPU.
         */
-       lint1 = LAPIC_LVT_DM_NMI;
+       lint1 = LAPIC_DLMODE_NMI;
        if (!CPU_IS_PRIMARY(curcpu()))
                lint1 |= LAPIC_LVT_MASKED;
-       lapic_writereg(LAPIC_LVINT1, lint1);
+       lapic_writereg(LAPIC_LVT_LINT1, lint1);
 
        for (i = 0; i < mp_nintr; i++) {
                mpi = &mp_intrs[i];
@@ -456,9 +456,9 @@
                                    "%s: WARNING: bad pin value %d\n",
                                    __func__, mpi->ioapic_pin);
                        if (mpi->ioapic_pin == 0)
-                               lapic_writereg(LAPIC_LVINT0, mpi->redir);
+                               lapic_writereg(LAPIC_LVT_LINT0, mpi->redir);
                        else
-                               lapic_writereg(LAPIC_LVINT1, mpi->redir);
+                               lapic_writereg(LAPIC_LVT_LINT1, mpi->redir);
                }
        }
 
@@ -588,10 +588,12 @@
         * then set divisor,
         * then unmask and set the vector.
         */
-       lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_LVTT_M);
+       lapic_writereg(LAPIC_LVT_TIMER,
+           LAPIC_LVT_TMM_PERIODIC | LAPIC_LVT_MASKED);
        lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
        lapic_writereg(LAPIC_ICR_TIMER, lapic_tval);
-       lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_TIMER_VECTOR);
+       lapic_writereg(LAPIC_LVT_TIMER,
+           LAPIC_LVT_TMM_PERIODIC | LAPIC_TIMER_VECTOR);
        lapic_eoi();
 }
 
@@ -627,7 +629,7 @@
         * Configure timer to one-shot, interrupt masked,
         * large positive number.
         */
-       lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_M);
+       lapic_writereg(LAPIC_LVT_TIMER, LAPIC_LVT_MASKED);
        lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
        lapic_writereg(LAPIC_ICR_TIMER, 0x80000000);
 
@@ -664,8 +666,8 @@
                lapic_tval = (lapic_per_second * 2) / hz;
                lapic_tval = (lapic_tval / 2) + (lapic_tval & 0x1);
 
-               lapic_writereg(LAPIC_LVTT, LAPIC_LVTT_TM | LAPIC_LVTT_M
-                   | LAPIC_TIMER_VECTOR);
+               lapic_writereg(LAPIC_LVT_TIMER, LAPIC_LVT_TMM_PERIODIC
+                   | LAPIC_LVT_MASKED | LAPIC_TIMER_VECTOR);
                lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
                lapic_writereg(LAPIC_ICR_TIMER, lapic_tval);
 
@@ -790,7 +792,7 @@
        i82489_icr_wait();
        x86_delay(10000);
        i82489_writereg(LAPIC_ICRLO,
-           LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
+           LAPIC_DLMODE_INIT | LAPIC_TRIGMODE_LEVEL | LAPIC_LEVEL_DEASSERT);
        i82489_icr_wait();
 
        if ((i82489_readreg(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0)
@@ -863,7 +865,7 @@
        x86_delay(10000);
 
        x2apic_write_icr(0,
-           LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT);
+           LAPIC_DLMODE_INIT | LAPIC_TRIGMODE_LEVEL | LAPIC_LEVEL_DEASSERT);
 
        return 0;
 }



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