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[src/trunk]: src/sys/arch/arm/amlogic Fix module clock rate in DDR52 mode and...



details:   https://anonhg.NetBSD.org/src/rev/8f96eb57f522
branches:  trunk
changeset: 998559:8f96eb57f522
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Apr 21 13:08:48 2019 +0000

description:
Fix module clock rate in DDR52 mode and support mmc-ddr-3_3v DT property

diffstat:

 sys/arch/arm/amlogic/mesongx_mmc.c |  10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diffs (38 lines):

diff -r 9f9b38acefbd -r 8f96eb57f522 sys/arch/arm/amlogic/mesongx_mmc.c
--- a/sys/arch/arm/amlogic/mesongx_mmc.c        Sun Apr 21 12:36:39 2019 +0000
+++ b/sys/arch/arm/amlogic/mesongx_mmc.c        Sun Apr 21 13:08:48 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongx_mmc.c,v 1.4 2019/03/16 12:52:47 jmcneill Exp $ */
+/* $NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.4 2019/03/16 12:52:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.5 2019/04/21 13:08:48 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -463,7 +463,7 @@
        best_sel = 0;
        best_div = 0;
 
-       const u_int target_rate = (freq * 1000) >> ddr;
+       const u_int target_rate = (freq * 1000) << ddr;
        for (sel = 0; sel <= 1; sel++) {
                const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]);
                for (div = 1; div <= 63; div++) {
@@ -541,6 +541,10 @@
        if (of_getprop_bool(sc->sc_phandle, "cap-mmc-highspeed"))
                saa.saa_caps |= SMC_CAPS_MMC_HIGHSPEED;
 
+       if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-3_3v")) {
+               saa.saa_caps |= SMC_CAPS_MMC_DDR52;
+       }
+
        if (of_getprop_bool(sc->sc_phandle, "mmc-ddr-1_8v")) {
                saa.saa_caps |= SMC_CAPS_MMC_DDR52;
                sc->sc_host_ocr |= MMC_OCR_1_65V_1_95V;



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