Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/arch/mips Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWR...



details:   https://anonhg.NetBSD.org/src/rev/7e93b616bdbd
branches:  trunk
changeset: 972946:7e93b616bdbd
user:      simonb <simonb%NetBSD.org@localhost>
date:      Sun Jun 14 06:50:31 2020 +0000

description:
Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register.  Probe correctly and save probed info somewhere we can
actually use it.  Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

diffstat:

 sys/arch/mips/include/locore.h    |  58 ++++++++++++++++++++++----------------
 sys/arch/mips/mips/cpu_subr.c     |  21 ++++++-------
 sys/arch/mips/mips/db_interface.c |   8 ++--
 sys/arch/mips/mips/mips_machdep.c |  34 +++++++++++-----------
 4 files changed, 65 insertions(+), 56 deletions(-)

diffs (truncated from 370 to 300 lines):

diff -r 8bf86609a040 -r 7e93b616bdbd sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h    Sun Jun 14 05:10:33 2020 +0000
+++ b/sys/arch/mips/include/locore.h    Sun Jun 14 06:50:31 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.106 2020/06/13 14:26:33 simonb Exp $ */
+/* $NetBSD: locore.h,v 1.107 2020/06/14 06:50:31 simonb Exp $ */
 
 /*
  * This file should not be included by MI code!!!
@@ -146,22 +146,23 @@
 #define        CPU_ARCH_MIPS32R2       (1 << 7)
 #define        CPU_ARCH_MIPS64R2       (1 << 8)
 
-#define        CPU_MIPS_R4K_MMU                0x0001
-#define        CPU_MIPS_NO_LLSC                0x0002
-#define        CPU_MIPS_CAUSE_IV               0x0004
-#define        CPU_MIPS_HAVE_SPECIAL_CCA       0x0008  /* Defaults to '3' if not set. */
-#define        CPU_MIPS_CACHED_CCA_MASK        0x0070
+#define        CPU_MIPS_R4K_MMU                0x00001
+#define        CPU_MIPS_NO_LLSC                0x00002
+#define        CPU_MIPS_CAUSE_IV               0x00004
+#define        CPU_MIPS_HAVE_SPECIAL_CCA       0x00008 /* Defaults to '3' if not set. */
+#define        CPU_MIPS_CACHED_CCA_MASK        0x00070
 #define        CPU_MIPS_CACHED_CCA_SHIFT        4
-#define        CPU_MIPS_DOUBLE_COUNT           0x0080  /* 1 cp0 count == 2 clock cycles */
-#define        CPU_MIPS_USE_WAIT               0x0100  /* Use "wait"-based cpu_idle() */
-#define        CPU_MIPS_NO_WAIT                0x0200  /* Inverse of previous, for mips32/64 */
-#define        CPU_MIPS_D_CACHE_COHERENT       0x0400  /* D-cache is fully coherent */
-#define        CPU_MIPS_I_D_CACHE_COHERENT     0x0800  /* I-cache funcs don't need to flush the D-cache */
-#define        CPU_MIPS_NO_LLADDR              0x1000
-#define        CPU_MIPS_HAVE_MxCR              0x2000  /* have mfcr, mtcr insns */
-#define        CPU_MIPS_LOONGSON2              0x4000
-#define        MIPS_NOT_SUPP                   0x8000
+#define        CPU_MIPS_DOUBLE_COUNT           0x00080 /* 1 cp0 count == 2 clock cycles */
+#define        CPU_MIPS_USE_WAIT               0x00100 /* Use "wait"-based cpu_idle() */
+#define        CPU_MIPS_NO_WAIT                0x00200 /* Inverse of previous, for mips32/64 */
+#define        CPU_MIPS_D_CACHE_COHERENT       0x00400 /* D-cache is fully coherent */
+#define        CPU_MIPS_I_D_CACHE_COHERENT     0x00800 /* I-cache funcs don't need to flush the D-cache */
+#define        CPU_MIPS_NO_LLADDR              0x01000
+#define        CPU_MIPS_HAVE_MxCR              0x02000 /* have mfcr, mtcr insns */
+#define        CPU_MIPS_LOONGSON2              0x04000
+#define        MIPS_NOT_SUPP                   0x08000
 #define        CPU_MIPS_HAVE_DSP               0x10000
+#define        CPU_MIPS_HAVE_USERLOCAL         0x20000
 
 #endif /* !_LOCORE */
 
@@ -181,8 +182,9 @@
 # define MIPS_HAS_CLOCK                0
 # define MIPS_HAS_LLSC         0
 # define MIPS_HAS_LLADDR       0
+# define MIPS_HAS_LMMI         0
 # define MIPS_HAS_DSP          0
-# define MIPS_HAS_LMMI         0
+# define MIPS_HAS_USERLOCAL    0
 
 #elif defined(MIPS3) || defined(MIPS4)
 
@@ -206,12 +208,14 @@
 #  define MIPS_HAS_LLSC                (mips_options.mips_has_llsc)
 # endif        /* _LOCORE */
 # define MIPS_HAS_LLADDR       ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
-# define MIPS_HAS_DSP          0
 # if defined(MIPS3_LOONGSON2)
 #  define MIPS_HAS_LMMI                ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0)
 # else
 #  define MIPS_HAS_LMMI                0
 # endif
+# define MIPS_HAS_DSP          0
+# define MIPS_HAS_USERLOCAL    0
+
 #elif defined(MIPS32)
 
 # define CPUISMIPS3            1
@@ -226,8 +230,9 @@
 # define MIPS_HAS_CLOCK                1
 # define MIPS_HAS_LLSC         1
 # define MIPS_HAS_LLADDR       ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+# define MIPS_HAS_LMMI         0
 # define MIPS_HAS_DSP          0
-# define MIPS_HAS_LMMI         0
+# define MIPS_HAS_USERLOCAL    0
 
 #elif defined(MIPS32R2)
 
@@ -243,8 +248,9 @@
 # define MIPS_HAS_CLOCK                1
 # define MIPS_HAS_LLSC         1
 # define MIPS_HAS_LLADDR       ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+# define MIPS_HAS_LMMI         0
 # define MIPS_HAS_DSP          (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
-# define MIPS_HAS_LMMI         0
+# define MIPS_HAS_USERLOCAL    (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
 
 #elif defined(MIPS64)
 
@@ -260,8 +266,9 @@
 # define MIPS_HAS_CLOCK                1
 # define MIPS_HAS_LLSC         1
 # define MIPS_HAS_LLADDR       ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+# define MIPS_HAS_LMMI         0
 # define MIPS_HAS_DSP          0
-# define MIPS_HAS_LMMI         0
+# define MIPS_HAS_USERLOCAL    0
 
 #elif defined(MIPS64R2)
 
@@ -277,8 +284,9 @@
 # define MIPS_HAS_CLOCK                1
 # define MIPS_HAS_LLSC         1
 # define MIPS_HAS_LLADDR       ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+# define MIPS_HAS_LMMI         0
 # define MIPS_HAS_DSP          (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
-# define MIPS_HAS_LMMI         0
+# define MIPS_HAS_USERLOCAL    (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
 
 #endif
 
@@ -297,6 +305,7 @@
 #endif
 #define        MIPS_HAS_LLADDR         ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
 #define MIPS_HAS_DSP           (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP)
+# define MIPS_HAS_USERLOCAL    (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_USERLOCAL)
 
 /* This test is ... rather bogus */
 #define        CPUISMIPS3      ((mips_options.mips_cpu_arch & \
@@ -309,7 +318,10 @@
 #define        CPUISMIPS32R2   ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0)
 #define        CPUISMIPS64     ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
 #define        CPUISMIPS64R2   ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0)
-#define        CPUISMIPSNN     ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
+#define        CPUISMIPSNN     ((mips_options.mips_cpu_arch & \
+       (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
+#define        CPUISMIPSNNR2   ((mips_options.mips_cpu_arch & \
+       (CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64R2)) != 0)
 #define        CPUIS64BITS     ((mips_options.mips_cpu_arch & \
        (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
 
@@ -866,8 +878,6 @@
 #define  MIPS_CP0FL_CONFIG5    __BIT(11) /* XXX probeable - shouldn't be hard coded */
 #define  MIPS_CP0FL_CONFIG6    __BIT(12) /* XXX probeable - shouldn't be hard coded */
 #define  MIPS_CP0FL_CONFIG7    __BIT(13) /* XXX probeable - shouldn't be hard coded */
-#define  MIPS_CP0FL_USERLOCAL  __BIT(14) /* XXX probeable - shouldn't be hard coded */
-#define  MIPS_CP0FL_HWRENA     __BIT(15) /* XXX probeable - shouldn't be hard coded */
 
 /*
  * cpu_cidflags defines, by company
diff -r 8bf86609a040 -r 7e93b616bdbd sys/arch/mips/mips/cpu_subr.c
--- a/sys/arch/mips/mips/cpu_subr.c     Sun Jun 14 05:10:33 2020 +0000
+++ b/sys/arch/mips/mips/cpu_subr.c     Sun Jun 14 06:50:31 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu_subr.c,v 1.47 2020/06/11 19:20:44 ad Exp $ */
+/*     $NetBSD: cpu_subr.c,v 1.48 2020/06/14 06:50:31 simonb Exp $     */
 
 /*-
  * Copyright (c) 2010, 2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.47 2020/06/11 19:20:44 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.48 2020/06/14 06:50:31 simonb Exp $");
 
 #include "opt_cputype.h"
 #include "opt_ddb.h"
@@ -209,14 +209,14 @@
        if ((cp0flags & MIPS_CP0FL_USE) == 0)
                return;
 
-       if (cp0flags & MIPS_CP0FL_HWRENA) {
+       if (CPUISMIPSNNR2) {
                mipsNN_cp0_hwrena_write(
-                   MIPS_HWRENA_UL
-                   |MIPS_HWRENA_CCRES
-                   |MIPS_HWRENA_CC
-                   |MIPS_HWRENA_SYNCI_STEP
-                   |MIPS_HWRENA_CPUNUM);
-               if (cp0flags & MIPS_CP0FL_USERLOCAL) {
+                   (MIPS_HAS_USERLOCAL ? MIPS_HWRENA_UL : 0)
+                   | MIPS_HWRENA_CCRES
+                   | MIPS_HWRENA_CC
+                   | MIPS_HWRENA_SYNCI_STEP
+                   | MIPS_HWRENA_CPUNUM);
+               if (MIPS_HAS_USERLOCAL) {
                        mipsNN_cp0_userlocal_write(curlwp->l_private);
                }
        }
@@ -1022,8 +1022,7 @@
 cpu_lwp_setprivate(lwp_t *l, void *v)
 {
 #if (MIPS32R2 + MIPS64R2) > 0
-       if (l == curlwp
-           && (mips_options.mips_cpu->cpu_cp0flags & MIPS_CP0FL_USERLOCAL)) {
+       if (l == curlwp && MIPS_HAS_USERLOCAL) {
                mipsNN_cp0_userlocal_write(v);
        }
 #endif
diff -r 8bf86609a040 -r 7e93b616bdbd sys/arch/mips/mips/db_interface.c
--- a/sys/arch/mips/mips/db_interface.c Sun Jun 14 05:10:33 2020 +0000
+++ b/sys/arch/mips/mips/db_interface.c Sun Jun 14 06:50:31 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: db_interface.c,v 1.82 2019/04/06 03:06:26 thorpej Exp $        */
+/*     $NetBSD: db_interface.c,v 1.83 2020/06/14 06:50:31 simonb Exp $ */
 
 /*
  * Mach Operating System
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.82 2019/04/06 03:06:26 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.83 2020/06/14 06:50:31 simonb Exp $");
 
 #include "opt_multiprocessor.h"
 #include "opt_cputype.h"       /* which mips CPUs do we support? */
@@ -466,9 +466,9 @@
                        SHOW32SEL(16, 6, "config6");
                if ((cp0flags & MIPS_CP0FL_CONFIG7) != 0)
                        SHOW32SEL(16, 7, "config7");
-               if ((cp0flags & MIPS_CP0FL_HWRENA) != 0)
+               if (CPUISMIPSNNR2)
                        SHOW32(7, "hwrena");
-               if ((cp0flags & MIPS_CP0FL_USERLOCAL) != 0)
+               if (MIPS_HAS_USERLOCAL)
                        SHOW32SEL(4, 2, "userlocal");
        } else {
                SHOW32(MIPS_COP_0_CONFIG, "config");
diff -r 8bf86609a040 -r 7e93b616bdbd sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Sun Jun 14 05:10:33 2020 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Sun Jun 14 06:50:31 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_machdep.c,v 1.287 2020/06/13 14:45:17 simonb Exp $        */
+/*     $NetBSD: mips_machdep.c,v 1.288 2020/06/14 06:50:31 simonb Exp $        */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.287 2020/06/13 14:45:17 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.288 2020/06/14 06:50:31 simonb Exp $");
 
 #define __INTR_PRIVATE
 #include "opt_cputype.h"
@@ -460,21 +460,21 @@
        { MIPS_PRID_CID_MTI, MIPS_24K, -1, -1,  -1, 0,
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
          0, "24K" },
        { MIPS_PRID_CID_MTI, MIPS_24KE, -1, -1, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
          0, "24KE" },
        { MIPS_PRID_CID_MTI, MIPS_34K, -1, -1,  -1, 0,
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
          0, "34K" },
@@ -482,21 +482,21 @@
          CPU_MIPS_HAVE_SPECIAL_CCA | (0 << CPU_MIPS_CACHED_CCA_SHIFT) |
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
          0, "74K" },
        { MIPS_PRID_CID_MTI, MIPS_1004K, -1, -1,        -1, 0,
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
          0, "1004K" },
        { MIPS_PRID_CID_MTI, MIPS_1074K, -1, -1,        -1, 0,
          MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
+         MIPS_CP0FL_EBASE |
          MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
          MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
          0, "1074K" },
@@ -659,7 +659,7 @@
        { MIPS_PRID_CID_CAVIUM, MIPS_CN50XX, -1, -1, -1, 0,
          MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
          MIPS_CP0FL_USE |
-         MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG | MIPS_CP0FL_HWRENA |



Home | Main Index | Thread Index | Old Index