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[src/trunk]: src/sys/arch/aarch64 - move aarch64 addressspace macros from pma...



details:   https://anonhg.NetBSD.org/src/rev/e0502d5d7043
branches:  trunk
changeset: 972014:e0502d5d7043
user:      ryo <ryo%NetBSD.org@localhost>
date:      Wed May 13 06:08:51 2020 +0000

description:
- move aarch64 addressspace macros from pmap.h to cpufunc.h
- rename ptr_strip_pac() to aarch64_strip_pac()

diffstat:

 sys/arch/aarch64/aarch64/db_trace.c |  11 ++--
 sys/arch/aarch64/aarch64/fault.c    |   5 +-
 sys/arch/aarch64/include/armreg.h   |  13 +-----
 sys/arch/aarch64/include/cpufunc.h  |  84 ++++++++++++++++++++++++++++++++++++-
 sys/arch/aarch64/include/pmap.h     |  72 +-------------------------------
 5 files changed, 94 insertions(+), 91 deletions(-)

diffs (285 lines):

diff -r 11c4c0bcf6c8 -r e0502d5d7043 sys/arch/aarch64/aarch64/db_trace.c
--- a/sys/arch/aarch64/aarch64/db_trace.c       Wed May 13 05:52:54 2020 +0000
+++ b/sys/arch/aarch64/aarch64/db_trace.c       Wed May 13 06:08:51 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_trace.c,v 1.9 2020/04/12 07:49:58 maxv Exp $ */
+/* $NetBSD: db_trace.c,v 1.10 2020/05/13 06:08:51 ryo Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -28,11 +28,12 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: db_trace.c,v 1.9 2020/04/12 07:49:58 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_trace.c,v 1.10 2020/05/13 06:08:51 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/proc.h>
 
+#include <aarch64/cpufunc.h>
 #include <aarch64/db_machdep.h>
 #include <aarch64/machdep.h>
 #include <aarch64/armreg.h>
@@ -236,7 +237,7 @@
                lastfp = lastlr = lr = fp = 0;
                db_read_bytes((db_addr_t)&tf->tf_pc, sizeof(lr), (char *)&lr);
                db_read_bytes((db_addr_t)&tf->tf_reg[29], sizeof(fp), (char *)&fp);
-               lr = ptr_strip_pac(lr);
+               lr = aarch64_strip_pac(lr);
 
                pr_traceaddr("fp", fp, lr - 4, flags, pr);
        }
@@ -252,7 +253,7 @@
                 */
                db_read_bytes(lastfp + 0, sizeof(fp), (char *)&fp);
                db_read_bytes(lastfp + 8, sizeof(lr), (char *)&lr);
-               lr = ptr_strip_pac(lr);
+               lr = aarch64_strip_pac(lr);
 
                if (!trace_user && IN_USER_VM_ADDRESS(lr))
                        break;
@@ -270,7 +271,7 @@
                        lr = fp = 0;
                        db_read_bytes((db_addr_t)&tf->tf_pc, sizeof(lr), (char *)&lr);
                        db_read_bytes((db_addr_t)&tf->tf_reg[29], sizeof(fp), (char *)&fp);
-                       lr = ptr_strip_pac(lr);
+                       lr = aarch64_strip_pac(lr);
 
                        /*
                         * no need to display the frame of el0_trap
diff -r 11c4c0bcf6c8 -r e0502d5d7043 sys/arch/aarch64/aarch64/fault.c
--- a/sys/arch/aarch64/aarch64/fault.c  Wed May 13 05:52:54 2020 +0000
+++ b/sys/arch/aarch64/aarch64/fault.c  Wed May 13 06:08:51 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fault.c,v 1.12 2020/02/29 21:34:37 ryo Exp $   */
+/*     $NetBSD: fault.c,v 1.13 2020/05/13 06:08:51 ryo Exp $   */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.12 2020/02/29 21:34:37 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fault.c,v 1.13 2020/05/13 06:08:51 ryo Exp $");
 
 #include "opt_compat_netbsd32.h"
 #include "opt_ddb.h"
@@ -40,6 +40,7 @@
 
 #include <uvm/uvm.h>
 
+#include <aarch64/cpufunc.h>
 #include <aarch64/frame.h>
 #include <aarch64/machdep.h>
 #include <aarch64/armreg.h>
diff -r 11c4c0bcf6c8 -r e0502d5d7043 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Wed May 13 05:52:54 2020 +0000
+++ b/sys/arch/aarch64/include/armreg.h Wed May 13 06:08:51 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.42 2020/05/11 03:00:57 ryo Exp $ */
+/* $NetBSD: armreg.h,v 1.43 2020/05/13 06:08:51 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -807,17 +807,6 @@
 #define        SCTLR_ATA               __BIT(43)
 #define        SCTLR_DSSBS             __BIT(44)
 
-#define        PTR_VA_RANGE_SELECT     __BIT(55)
-#define        PTR_PAC_MASK            (__BITS(63,56) | __BITS(54, 48))
-
-static __inline uint64_t
-ptr_strip_pac(uint64_t __val)
-{
-       if (__val & PTR_VA_RANGE_SELECT)
-               return __val | PTR_PAC_MASK;
-       return __val & ~PTR_PAC_MASK;
-}
-
 // current EL stack pointer
 static __inline uint64_t
 reg_sp_read(void)
diff -r 11c4c0bcf6c8 -r e0502d5d7043 sys/arch/aarch64/include/cpufunc.h
--- a/sys/arch/aarch64/include/cpufunc.h        Wed May 13 05:52:54 2020 +0000
+++ b/sys/arch/aarch64/include/cpufunc.h        Wed May 13 06:08:51 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.h,v 1.12 2020/04/12 07:49:58 maxv Exp $        */
+/*     $NetBSD: cpufunc.h,v 1.13 2020/05/13 06:08:51 ryo Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -166,4 +166,86 @@
 
 #endif /* _KERNEL */
 
+/* definitions of TAG and PAC in pointers */
+#define AARCH64_ADDRTOP_TAG            __BIT(55)       /* ECR_EL1.TBI[01]=1 */
+#define AARCH64_ADDRTOP_MSB            __BIT(63)       /* ECR_EL1.TBI[01]=0 */
+#define AARCH64_ADDRESS_TAG_MASK       __BITS(63,56)   /* if TCR.TBI[01]=1 */
+#define AARCH64_ADDRESS_PAC_MASK       __BITS(54,48)   /* depend on VIRT_BIT */
+#define AARCH64_ADDRESS_TAGPAC_MASK    \
+                       (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK)
+
+#ifdef _KERNEL
+/*
+ * Which is the address space of this VA?
+ * return the space considering TBI. (PAC is not yet)
+ *
+ * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}?
+ */
+#define AARCH64_ADDRSPACE_LOWER                        0       /* -> TTBR0 */
+#define AARCH64_ADDRSPACE_UPPER                        1       /* -> TTBR1 */
+#define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE     -1      /* certainly fault */
+#define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE     -2      /* certainly fault */
+static inline int
+aarch64_addressspace(vaddr_t va)
+{
+       uint64_t addrtop, tbi;
+
+       addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
+       tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
+       if (reg_tcr_el1_read() & tbi) {
+               if (addrtop == 0) {
+                       /* lower address, and TBI0 enabled */
+                       if ((va & AARCH64_ADDRESS_PAC_MASK) != 0)
+                               return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
+                       return AARCH64_ADDRSPACE_LOWER;
+               }
+               /* upper address, and TBI1 enabled */
+               if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK)
+                       return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
+               return AARCH64_ADDRSPACE_UPPER;
+       }
+
+       addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB;
+       if (addrtop == 0) {
+               /* lower address, and TBI0 disabled */
+               if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0)
+                       return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
+               return AARCH64_ADDRSPACE_LOWER;
+       }
+       /* upper address, and TBI1 disabled */
+       if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK)
+               return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
+       return AARCH64_ADDRSPACE_UPPER;
+}
+
+static inline vaddr_t
+aarch64_untag_address(vaddr_t va)
+{
+       uint64_t addrtop, tbi;
+
+       addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
+       tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
+       if (reg_tcr_el1_read() & tbi) {
+               if (addrtop == 0) {
+                       /* lower address, and TBI0 enabled */
+                       return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK;
+               }
+               /* upper address, and TBI1 enabled */
+               return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK;
+       }
+
+       /* TBI[01] is disabled, nothing to do */
+       return va;
+}
+
+#endif /* _KERNEL */
+
+static __inline uint64_t
+aarch64_strip_pac(uint64_t __val)
+{
+       if (__val & AARCH64_ADDRTOP_TAG)
+               return __val | AARCH64_ADDRESS_TAGPAC_MASK;
+       return __val & ~AARCH64_ADDRESS_TAGPAC_MASK;
+}
+
 #endif /* _AARCH64_CPUFUNC_H_ */
diff -r 11c4c0bcf6c8 -r e0502d5d7043 sys/arch/aarch64/include/pmap.h
--- a/sys/arch/aarch64/include/pmap.h   Wed May 13 05:52:54 2020 +0000
+++ b/sys/arch/aarch64/include/pmap.h   Wed May 13 06:08:51 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.37 2020/04/08 00:13:40 ryo Exp $ */
+/* $NetBSD: pmap.h,v 1.38 2020/05/13 06:08:51 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -282,76 +282,6 @@
        return pflag;
 }
 
-/*
- * Which is the address space of this VA?
- * return the space considering TBI. (PAC is not yet)
- *
- * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}?
- */
-#define AARCH64_ADDRTOP_TAG            __BIT(55)       /* ECR_EL1.TBI[01]=1 */
-#define AARCH64_ADDRTOP_MSB            __BIT(63)       /* ECR_EL1.TBI[01]=0 */
-#define AARCH64_ADDRESS_TAG_MASK       __BITS(63,56)   /* if TCR.TBI[01]=1 */
-#define AARCH64_ADDRESS_PAC_MASK       __BITS(54,48)   /* depend on VIRT_BIT */
-#define AARCH64_ADDRESS_TAGPAC_MASK    \
-                       (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK)
-
-#define AARCH64_ADDRSPACE_LOWER                        0       /* -> TTBR0 */
-#define AARCH64_ADDRSPACE_UPPER                        1       /* -> TTBR1 */
-#define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE     -1      /* certainly fault */
-#define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE     -2      /* certainly fault */
-static inline int
-aarch64_addressspace(vaddr_t va)
-{
-       uint64_t addrtop, tbi;
-
-       addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
-       tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
-       if (reg_tcr_el1_read() & tbi) {
-               if (addrtop == 0) {
-                       /* lower address, and TBI0 enabled */
-                       if ((va & AARCH64_ADDRESS_PAC_MASK) != 0)
-                               return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
-                       return AARCH64_ADDRSPACE_LOWER;
-               }
-               /* upper address, and TBI1 enabled */
-               if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK)
-                       return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
-               return AARCH64_ADDRSPACE_UPPER;
-       }
-
-       addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB;
-       if (addrtop == 0) {
-               /* lower address, and TBI0 disabled */
-               if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0)
-                       return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
-               return AARCH64_ADDRSPACE_LOWER;
-       }
-       /* upper address, and TBI1 disabled */
-       if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK)
-               return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
-       return AARCH64_ADDRSPACE_UPPER;
-}
-
-static inline vaddr_t
-aarch64_untag_address(vaddr_t va)
-{
-       uint64_t addrtop, tbi;
-
-       addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
-       tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
-       if (reg_tcr_el1_read() & tbi) {
-               if (addrtop == 0) {
-                       /* lower address, and TBI0 enabled */
-                       return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK;
-               }
-               /* upper address, and TBI1 enabled */
-               return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK;
-       }
-
-       /* TBI[01] is disabled, nothing to do */
-       return va;
-}
-
 #define pmap_phys_address(pa)          aarch64_ptob((pa))
 #define pmap_mmap_flags(ppn)           aarch64_mmap_flags((ppn))
 



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