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[src/trunk]: src/sys/arch/arm/samsung Support Exynos 5410 GPIO



details:   https://anonhg.NetBSD.org/src/rev/2e8cdf27ce5c
branches:  trunk
changeset: 970312:2e8cdf27ce5c
user:      skrll <skrll%NetBSD.org@localhost>
date:      Fri Mar 20 06:38:16 2020 +0000

description:
Support Exynos 5410 GPIO

diffstat:

 sys/arch/arm/samsung/exynos_gpio.c    |  129 ++++++++++++++++++++++++++++-----
 sys/arch/arm/samsung/exynos_pinctrl.c |   32 +++++---
 sys/arch/arm/samsung/exynos_pinctrl.h |   32 ++++++++
 sys/arch/arm/samsung/exynos_var.h     |   12 ++-
 4 files changed, 169 insertions(+), 36 deletions(-)

diffs (truncated from 382 to 300 lines):

diff -r 4b76c3dd66e6 -r 2e8cdf27ce5c sys/arch/arm/samsung/exynos_gpio.c
--- a/sys/arch/arm/samsung/exynos_gpio.c        Fri Mar 20 06:35:59 2020 +0000
+++ b/sys/arch/arm/samsung/exynos_gpio.c        Fri Mar 20 06:38:16 2020 +0000
@@ -1,11 +1,11 @@
-/*     $NetBSD: exynos_gpio.c,v 1.28 2020/03/20 06:35:59 skrll Exp $ */
+/*     $NetBSD: exynos_gpio.c,v 1.29 2020/03/20 06:38:16 skrll Exp $ */
 
 /*-
-* Copyright (c) 2014 The NetBSD Foundation, Inc.
+* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
-* by Reinoud Zandijk
+* by Reinoud Zandijk, and by Nick Hudson
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -34,7 +34,7 @@
 #include "gpio.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.28 2020/03/20 06:35:59 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_gpio.c,v 1.29 2020/03/20 06:38:16 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -84,7 +84,30 @@
                .bank_bits = b, \
        }
 
-static struct exynos_gpio_bank exynos5_banks[] = {
+#define GPIO_GRP_INTR(o, n, b, i)                      \
+       {                                               \
+               .bank_name = #n,                        \
+               .bank_core_offset = GPIO_REG(v,s,o),    \
+               .bank_bits = b,                         \
+       }
+
+#define GPIO_GRP_NONE(o, n, b) \
+       { \
+               .bank_name = #n, \
+               .bank_core_offset = GPIO_REG(v,s,o), \
+               .bank_bits = b, \
+       }
+
+#define GPIO_GRP_WAKEUP(o, n, b, i)                    \
+       {                                               \
+               .bank_name = #n,                        \
+               .bank_core_offset = GPIO_REG(v,s,o),    \
+               .bank_bits = b,                         \
+       }
+
+
+
+static struct exynos_gpio_bank exynos5420_banks[] = {
        GPIO_GRP(5, MUXA, 0x0000, gpy7, 8),
        GPIO_GRP(5, MUXA, 0x0C00, gpx0, 8),
        GPIO_GRP(5, MUXA, 0x0C20, gpx1, 8),
@@ -125,10 +148,78 @@
        GPIO_GRP(5, MUXD, 0x0100, gph0, 4),
 
        GPIO_GRP(5, MUXE, 0x0000, gpz, 7),
+};
 
+struct exynos_pinctrl_banks exynos5420_pinctrl_banks = {
+       .epb_banks = exynos5420_banks,
+       .epb_nbanks = __arraycount(exynos5420_banks)
 };
 
-struct exynos_gpio_bank *exynos_gpio_banks = exynos5_banks;
+static struct exynos_gpio_bank exynos5410_banks[] = {
+       /* pin-controller 0 */
+       GPIO_GRP_INTR(0x000, gpa0, 8, 0x00),
+       GPIO_GRP_INTR(0x020, gpa1, 6, 0x04),
+       GPIO_GRP_INTR(0x040, gpa2, 8, 0x08),
+       GPIO_GRP_INTR(0x060, gpb0, 5, 0x0c),
+       GPIO_GRP_INTR(0x080, gpb1, 5, 0x10),
+       GPIO_GRP_INTR(0x0A0, gpb2, 4, 0x14),
+       GPIO_GRP_INTR(0x0C0, gpb3, 4, 0x18),
+       GPIO_GRP_INTR(0x0E0, gpc0, 7, 0x1c),
+       GPIO_GRP_INTR(0x100, gpc3, 4, 0x20),
+       GPIO_GRP_INTR(0x120, gpc1, 7, 0x24),
+       GPIO_GRP_INTR(0x140, gpc2, 7, 0x28),
+       GPIO_GRP_INTR(0x180, gpd1, 8, 0x2c),
+       GPIO_GRP_INTR(0x1A0, gpe0, 8, 0x30),
+       GPIO_GRP_INTR(0x1C0, gpe1, 2, 0x34),
+       GPIO_GRP_INTR(0x1E0, gpf0, 6, 0x38),
+       GPIO_GRP_INTR(0x200, gpf1, 8, 0x3c),
+       GPIO_GRP_INTR(0x220, gpg0, 8, 0x40),
+       GPIO_GRP_INTR(0x240, gpg1, 8, 0x44),
+       GPIO_GRP_INTR(0x260, gpg2, 2, 0x48),
+       GPIO_GRP_INTR(0x280, gph0, 4, 0x4c),
+       GPIO_GRP_INTR(0x2A0, gph1, 8, 0x50),
+       GPIO_GRP_NONE(0x160, gpm5, 2),
+       GPIO_GRP_NONE(0x2C0, gpm7, 8),
+       GPIO_GRP_NONE(0x2E0, gpy0, 6),
+       GPIO_GRP_NONE(0x300, gpy1, 4),
+       GPIO_GRP_NONE(0x320, gpy2, 6),
+       GPIO_GRP_NONE(0x340, gpy3, 8),
+       GPIO_GRP_NONE(0x360, gpy4, 8),
+       GPIO_GRP_NONE(0x380, gpy5, 8),
+       GPIO_GRP_NONE(0x3A0, gpy6, 8),
+       GPIO_GRP_NONE(0x3C0, gpy7, 8),
+       GPIO_GRP_WAKEUP(0xC00, gpx0, 8, 0x00),
+       GPIO_GRP_WAKEUP(0xC20, gpx1, 8, 0x04),
+       GPIO_GRP_WAKEUP(0xC40, gpx2, 8, 0x08),
+       GPIO_GRP_WAKEUP(0xC60, gpx3, 8, 0x0c),
+
+       /* pin-controller 1 */
+       GPIO_GRP_INTR(0x000, gpj0, 5, 0x00),
+       GPIO_GRP_INTR(0x020, gpj1, 8, 0x04),
+       GPIO_GRP_INTR(0x040, gpj2, 8, 0x08),
+       GPIO_GRP_INTR(0x060, gpj3, 8, 0x0c),
+       GPIO_GRP_INTR(0x080, gpj4, 2, 0x10),
+       GPIO_GRP_INTR(0x0A0, gpk0, 8, 0x14),
+       GPIO_GRP_INTR(0x0C0, gpk1, 8, 0x18),
+       GPIO_GRP_INTR(0x0E0, gpk2, 8, 0x1c),
+       GPIO_GRP_INTR(0x100, gpk3, 7, 0x20),
+
+       /* pin-controller 2 */
+       GPIO_GRP_INTR(0x000, gpv0, 8, 0x00),
+       GPIO_GRP_INTR(0x020, gpv1, 8, 0x04),
+       GPIO_GRP_INTR(0x060, gpv2, 8, 0x08),
+       GPIO_GRP_INTR(0x080, gpv3, 8, 0x0c),
+       GPIO_GRP_INTR(0x0C0, gpv4, 2, 0x10),
+
+       /* pin-controller 2 */
+       GPIO_GRP_INTR(0x000, gpz, 7, 0x00),
+};
+
+struct exynos_pinctrl_banks exynos5410_pinctrl_banks = {
+       .epb_banks = exynos5410_banks,
+       .epb_nbanks = __arraycount(exynos5410_banks)
+};
+
 
 static int exynos_gpio_pin_read(void *, int);
 static void exynos_gpio_pin_write(void *, int, int);
@@ -275,14 +366,14 @@
 exynos_gpio_bank_config(struct exynos_pinctrl_softc * parent,
                        const struct fdt_attach_args *faa, int node)
 {
-       struct exynos_gpio_bank *bank = kmem_zalloc(sizeof(*bank), KM_SLEEP);
        struct exynos_gpio_softc *sc = kmem_zalloc(sizeof(*sc), KM_SLEEP);
        struct gpiobus_attach_args gba;
        struct gpio_chipset_tag *gc_tag;
        char result[64];
 
        OF_getprop(node, "name", result, sizeof(result));
-       bank = exynos_gpio_bank_lookup(result);
+       struct exynos_gpio_bank *bank =
+           exynos_gpio_bank_lookup(parent->sc_epb, result);
        if (bank == NULL) {
                aprint_error_dev(parent->sc_dev, "no bank found for %s\n",
                    result);
@@ -303,9 +394,11 @@
        gba.gba_gc = &bank->bank_gc;
        gba.gba_pins = bank->bank_pins;
        gba.gba_npins = bank->bank_bits;
+
        bank->bank_sc = sc;
        bank->bank_dev = config_found_ia(parent->sc_dev, "gpiobus", &gba,
                                         exynos_gpio_cfprint);
+       bank->bank_dev->dv_private = sc;
 
        /* read in our initial settings */
        bank->bank_cfg.cfg = GPIO_READ(bank, EXYNOS_GPIO_CON);
@@ -325,12 +418,12 @@
  * the '-', or the four character string if the dash is not present.
  */
 struct exynos_gpio_bank *
-exynos_gpio_bank_lookup(const char *name)
+exynos_gpio_bank_lookup(struct exynos_pinctrl_banks *epb,  const char *name)
 {
        struct exynos_gpio_bank *bank;
 
-       for (u_int n = 0; n < __arraycount(exynos5_banks); n++) {
-               bank = &exynos_gpio_banks[n];
+       for (u_int n = 0; n < epb->epb_nbanks; n++) {
+               bank = &epb->epb_banks[n];
                if (!strncmp(bank->bank_name, name,
                             strlen(bank->bank_name))) {
                        return bank;
@@ -357,25 +450,17 @@
 static void *
 exynos_gpio_fdt_acquire(device_t dev, const void *data, size_t len, int flags)
 {
-       const u_int *cells = data;
-       struct exynos_gpio_bank *bank = NULL;
        struct exynos_gpio_pin *gpin;
-       int n;
 
        if (len != 12)
                return NULL;
 
+       const u_int *cells = data;
        const int pin = be32toh(cells[1]) & 0x0f;
        const int actlo = be32toh(cells[2]) & 0x01;
 
-       for (n = 0; n < __arraycount(exynos5_banks); n++) {
-               if (exynos_gpio_banks[n].bank_dev == dev) {
-                       bank = &exynos_gpio_banks[n];
-                       break;
-               }
-       }
-       if (bank == NULL)
-               return NULL;
+       struct exynos_gpio_softc *bank_sc = device_private(dev);
+       struct exynos_gpio_bank * const bank = bank_sc->sc_bank;
 
        gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
        gpin->pin_sc = bank->bank_sc;
diff -r 4b76c3dd66e6 -r 2e8cdf27ce5c sys/arch/arm/samsung/exynos_pinctrl.c
--- a/sys/arch/arm/samsung/exynos_pinctrl.c     Fri Mar 20 06:35:59 2020 +0000
+++ b/sys/arch/arm/samsung/exynos_pinctrl.c     Fri Mar 20 06:38:16 2020 +0000
@@ -1,11 +1,11 @@
-/*     $NetBSD: exynos_pinctrl.c,v 1.16 2020/03/17 21:24:30 skrll Exp $ */
+/*     $NetBSD: exynos_pinctrl.c,v 1.17 2020/03/20 06:38:16 skrll Exp $ */
 
 /*-
-* Copyright (c) 2015 The NetBSD Foundation, Inc.
+* Copyright (c) 2015, 2020 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
-* by Marty Fouts
+* by Marty Fouts, and by Nick Hudson
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -34,7 +34,7 @@
 #include "gpio.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.16 2020/03/17 21:24:30 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.17 2020/03/20 06:38:16 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -72,15 +72,19 @@
 CFATTACH_DECL_NEW(exynos_pinctrl, sizeof(struct exynos_pinctrl_softc),
        exynos_pinctrl_match, exynos_pinctrl_attach, NULL, NULL);
 
+
+static const struct of_compat_data compat_data[] = {
+       { "samsung,exynos5410-pinctrl", (uintptr_t)&exynos5410_pinctrl_banks },
+       { "samsung,exynos5420-pinctrl", (uintptr_t)&exynos5420_pinctrl_banks },
+       { NULL }
+};
+
 static int
 exynos_pinctrl_match(device_t parent, cfdata_t cf, void *aux)
 {
-       const char * const compatible[] = {
-           "samsung,exynos5410-pinctrl",
-           "samsung,exynos5420-pinctrl",
-           NULL };
        struct fdt_attach_args * const faa = aux;
-       return of_match_compatible(faa->faa_phandle, compatible);
+
+       return of_match_compat_data(faa->faa_phandle, compat_data);
 }
 
 static void
@@ -99,9 +103,12 @@
                return;
        }
 
-       aprint_normal(" pinctl @ 0x%08x ", (uint)addr);
+       aprint_normal(" pinctrl @ 0x%08x ", (uint)addr);
+       self->dv_private = sc;
        sc->sc_dev = self;
        sc->sc_bst = faa->faa_bst;
+       sc->sc_epb = (struct exynos_pinctrl_banks *)of_search_compatible(faa->faa_phandle, compat_data)->data;
+
        error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
        if (error) {
                aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
@@ -121,7 +128,7 @@
 
                if (of_hasprop(child, "samsung,pins")) {
                        fdtbus_register_pinctrl_config(self, child,
-                                                      &exynos_pinctrl_controller_func);
+                           &exynos_pinctrl_controller_func);
                }
        }
 }
@@ -155,6 +162,7 @@
 exynos_do_config(struct exynos_pinctrl_config *pc)
 {
        struct exynos_gpio_pin_cfg *gc = &pc->pc_pincfg;
+       struct exynos_pinctrl_banks *epb = pc->pc_sc->sc_epb;
        struct exynos_gpio_bank *bank;
        const char *pins;
        int pin;
@@ -166,7 +174,7 @@
        for (pins = fdtbus_get_string(pc->pc_phandle, "samsung,pins");
             pins_len > 0;
             pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) {



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