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[src/trunk]: src Import rge(4) from OpenBSD for Realtek's RTL8125 based 2.5Gb...



details:   https://anonhg.NetBSD.org/src/rev/928b6145fe67
branches:  trunk
changeset: 968299:928b6145fe67
user:      sevan <sevan%NetBSD.org@localhost>
date:      Sat Jan 11 20:56:50 2020 +0000

description:
Import rge(4) from OpenBSD for Realtek's RTL8125 based 2.5GbE network cards.

diffstat:

 share/man/man4/rge.4    |    56 +
 sys/dev/pci/if_rge.c    |  2006 +++++++++++++++++++++++++++++++++++++++++++++++
 sys/dev/pci/if_rgereg.h |  1864 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 3926 insertions(+), 0 deletions(-)

diffs (truncated from 3938 to 300 lines):

diff -r 6c393cd7eb36 -r 928b6145fe67 share/man/man4/rge.4
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/share/man/man4/rge.4      Sat Jan 11 20:56:50 2020 +0000
@@ -0,0 +1,56 @@
+.\" $NetBSD: rge.4,v 1.1 2020/01/11 20:56:50 sevan Exp $
+.\" $OpenBSD: rge.4,v 1.2 2019/11/18 22:09:59 jmc Exp $
+.\"
+.\" Copyright (c) 2019 Kevin Lo <kevlo%openbsd.org@localhost>
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate: November 18 2019 $
+.Dt RGE 4
+.Os
+.Sh NAME
+.Nm rge
+.Nd Realtek 8125 PCI Express 2.5Gb Ethernet device
+.Sh SYNOPSIS
+.Cd "rge* at pci?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCI Express 2.5Gb Ethernet adapters based
+on the Realtek RTL8125 Ethernet controller, including the following:
+.Pp
+.Bl -bullet -offset indent -compact
+.It
+Realtek RTL8125 2.5GbE Adapter (2500baseT)
+.It
+Rivet Networks Killer E3000 Adapter (2500baseT)
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr ifmedia 4 ,
+.Xr intro 4 ,
+.Xr netintro 4 ,
+.Xr pci 4 ,
+.Xr hostname.if 5 ,
+.Xr ifconfig 8
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 6.6 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver was written by
+.An Kevin Lo Aq Mt kevlo%openbsd.org@localhost .
diff -r 6c393cd7eb36 -r 928b6145fe67 sys/dev/pci/if_rge.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/pci/if_rge.c      Sat Jan 11 20:56:50 2020 +0000
@@ -0,0 +1,2006 @@
+/*     $NetBSD: if_rge.c,v 1.1 2020/01/11 20:56:51 sevan Exp $ */
+/*     $OpenBSD: if_rge.c,v 1.2 2020/01/02 09:00:45 kevlo Exp $        */
+
+/*
+ * Copyright (c) 2019 Kevin Lo <kevlo%openbsd.org@localhost>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "bpfilter.h"
+#include "vlan.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/device.h>
+#include <sys/endian.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/mii/mii.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/if_rgereg.h>
+
+int            rge_match(struct device *, void *, void *);
+void           rge_attach(struct device *, struct device *, void *);
+int            rge_intr(void *);
+int            rge_encap(struct rge_softc *, struct mbuf *, int);
+int            rge_ioctl(struct ifnet *, u_long, caddr_t);
+void           rge_start(struct ifqueue *);
+void           rge_watchdog(struct ifnet *);
+int            rge_init(struct ifnet *);
+void           rge_stop(struct ifnet *);
+int            rge_ifmedia_upd(struct ifnet *);
+void           rge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+int            rge_allocmem(struct rge_softc *);
+int            rge_newbuf(struct rge_softc *, int);
+void           rge_discard_rxbuf(struct rge_softc *, int);
+int            rge_rx_list_init(struct rge_softc *);
+void           rge_tx_list_init(struct rge_softc *);
+int            rge_rxeof(struct rge_softc *);
+int            rge_txeof(struct rge_softc *);
+void           rge_reset(struct rge_softc *);
+void           rge_iff(struct rge_softc *);
+void           rge_set_phy_power(struct rge_softc *, int);
+void           rge_phy_config(struct rge_softc *);
+void           rge_set_macaddr(struct rge_softc *, const uint8_t *);
+void           rge_get_macaddr(struct rge_softc *, uint8_t *);
+void           rge_hw_init(struct rge_softc *);
+void           rge_disable_phy_ocp_pwrsave(struct rge_softc *);
+void           rge_patch_phy_mcu(struct rge_softc *, int);
+void           rge_add_media_types(struct rge_softc *);
+void           rge_config_imtype(struct rge_softc *, int);
+void           rge_disable_sim_im(struct rge_softc *);
+void           rge_setup_sim_im(struct rge_softc *);
+void           rge_setup_intr(struct rge_softc *, int);
+void           rge_exit_oob(struct rge_softc *);
+void           rge_write_csi(struct rge_softc *, uint32_t, uint32_t);
+uint32_t       rge_read_csi(struct rge_softc *, uint32_t);
+void           rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t);
+uint16_t       rge_read_mac_ocp(struct rge_softc *, uint16_t);
+void           rge_write_ephy(struct rge_softc *, uint16_t, uint16_t);
+void           rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t);
+void           rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t);
+uint16_t       rge_read_phy_ocp(struct rge_softc *, uint16_t);
+int            rge_get_link_status(struct rge_softc *);
+void           rge_txstart(void *);
+void           rge_tick(void *);
+void           rge_link_state(struct rge_softc *);
+
+static const struct {
+       uint16_t reg;
+       uint16_t val;
+}  rtl8125_def_bps[] = {
+       RTL8125_DEF_BPS
+}, rtl8125_mac_cfg2_ephy[] = {
+       RTL8125_MAC_CFG2_EPHY
+}, rtl8125_mac_cfg2_mcu[] = {
+       RTL8125_MAC_CFG2_MCU
+}, rtl8125_mac_cfg3_ephy[] = {
+       RTL8125_MAC_CFG3_EPHY
+}, rtl8125_mac_cfg3_mcu[] = {
+       RTL8125_MAC_CFG3_MCU
+};
+
+struct cfattach rge_ca = {
+       sizeof(struct rge_softc), rge_match, rge_attach
+};
+
+struct cfdriver rge_cd = {
+       NULL, "rge", DV_IFNET
+};
+
+const struct pci_matchid rge_devices[] = {
+       { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000 },
+       { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125 }
+};
+
+int
+rge_match(struct device *parent, void *match, void *aux)
+{
+       return (pci_matchbyid((struct pci_attach_args *)aux, rge_devices,
+           nitems(rge_devices)));
+}
+
+void
+rge_attach(struct device *parent, struct device *self, void *aux)
+{
+       struct rge_softc *sc = (struct rge_softc *)self;
+       struct pci_attach_args *pa = aux;
+       pci_chipset_tag_t pc = pa->pa_pc;
+       pci_intr_handle_t ih;
+       const char *intrstr = NULL;
+       struct ifnet *ifp;
+       pcireg_t reg;
+       uint32_t hwrev;
+       uint8_t eaddr[ETHER_ADDR_LEN];
+       int offset;
+
+       pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
+
+       /* 
+        * Map control/status registers.
+        */
+       if (pci_mapreg_map(pa, RGE_PCI_BAR2, PCI_MAPREG_TYPE_MEM |
+           PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle,
+           NULL, &sc->rge_bsize, 0)) {
+               if (pci_mapreg_map(pa, RGE_PCI_BAR1, PCI_MAPREG_TYPE_MEM |
+                   PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag,
+                   &sc->rge_bhandle, NULL, &sc->rge_bsize, 0)) {
+                       if (pci_mapreg_map(pa, RGE_PCI_BAR0, PCI_MAPREG_TYPE_IO,
+                           0, &sc->rge_btag, &sc->rge_bhandle, NULL,
+                           &sc->rge_bsize, 0)) {
+                               printf(": can't map mem or i/o space\n");
+                               return;
+                       }
+               }
+       }
+
+       /* 
+        * Allocate interrupt.
+        */
+       if (pci_intr_map_msi(pa, &ih) == 0)
+               sc->rge_flags |= RGE_FLAG_MSI;
+       else if (pci_intr_map(pa, &ih) != 0) {
+               printf(": couldn't map interrupt\n");
+               return;
+       }
+       intrstr = pci_intr_string(pc, ih);
+       sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, rge_intr,
+           sc, sc->sc_dev.dv_xname);
+       if (sc->sc_ih == NULL) {
+               printf(": couldn't establish interrupt");
+               if (intrstr != NULL)
+                       printf(" at %s", intrstr);
+               printf("\n");
+               return;
+       }
+       printf(": %s", intrstr);
+
+       sc->sc_dmat = pa->pa_dmat;
+       sc->sc_pc = pa->pa_pc;
+       sc->sc_tag = pa->pa_tag;
+
+       /* Determine hardware revision */
+       hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV;
+       switch (hwrev) {
+       case 0x60800000:
+               sc->rge_type = MAC_CFG2;
+               break;
+       case 0x60900000:
+               sc->rge_type = MAC_CFG3;
+               break;
+       default:
+               printf(": unknown version 0x%08x\n", hwrev);
+               return;
+       }
+
+       rge_config_imtype(sc, RGE_IMTYPE_SIM);
+
+       /* 
+        * PCI Express check.
+        */
+       if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
+           &offset, NULL)) {
+               /* Disable PCIe ASPM and ECPM. */
+               reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+                   offset + PCI_PCIE_LCSR);
+               reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
+                   PCI_PCIE_LCSR_ECPM);
+               pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCI_PCIE_LCSR,
+                   reg);
+       }
+
+       rge_exit_oob(sc);
+       rge_hw_init(sc);
+
+       rge_get_macaddr(sc, eaddr);
+       printf(", address %s\n", ether_sprintf(eaddr));
+
+       memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN);
+
+       rge_set_phy_power(sc, 1);
+       rge_phy_config(sc);
+
+       if (rge_allocmem(sc))
+               return;



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