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[src/netbsd-9]: src/usr.sbin/cpuctl/arch Pull up the following revisions (all...



details:   https://anonhg.NetBSD.org/src/rev/8d5332dd281e
branches:  netbsd-9
changeset: 963993:8d5332dd281e
user:      martin <martin%NetBSD.org@localhost>
date:      Fri Jul 10 11:20:29 2020 +0000

description:
Pull up the following revisions (all via patch) requested by msaitoh in
ticket #995:

        usr.sbin/cpuctl/Makefile                        1.9
        usr.sbin/cpuctl/arch/cpuctl_i386.h              1.5
        usr.sbin/cpuctl/arch/i386.c                     1.111-1.113
        usr.sbin/cpuctl/cpuctl.c                        1.31
        usr.sbin/cpuctl/cpuctl.h                        1.7
        sys/arch/x86/x86/identcpu_subr.c                1.1-1.7

- Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel
  processors.
- Add 0xa5 and 0xa6 for Comet Lake.
- Rename ci_cpuid_level to ci_max_cpuid and ci_cpuid_extlevel to
  ci_max_ext_cpuid to match x86/include/cpu.h. No functional change.
- Sort some entries.
- Add comment.

diffstat:

 sys/arch/x86/x86/identcpu_subr.c   |  145 +++++++++++++++++++++++++++++++++++++
 usr.sbin/cpuctl/Makefile           |    8 +-
 usr.sbin/cpuctl/arch/cpuctl_i386.h |   48 +++++++++++-
 usr.sbin/cpuctl/arch/i386.c        |  104 ++++++++-----------------
 usr.sbin/cpuctl/cpuctl.c           |    5 +-
 usr.sbin/cpuctl/cpuctl.h           |    5 +-
 6 files changed, 241 insertions(+), 74 deletions(-)

diffs (truncated from 596 to 300 lines):

diff -r b333bc5a0244 -r 8d5332dd281e sys/arch/x86/x86/identcpu_subr.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/x86/x86/identcpu_subr.c  Fri Jul 10 11:20:29 2020 +0000
@@ -0,0 +1,145 @@
+/* $NetBSD: identcpu_subr.c,v 1.7.2.2 2020/07/10 11:20:29 martin Exp $ */
+
+/*-
+ * Copyright (c) 2020 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Masanobu SAITOH.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Subroutines for CPU.
+ * This file is shared between kernel and userland.
+ * See src/usr.sbin/cpuctl/{Makefile, arch/i386.c}).
+ */
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.7.2.2 2020/07/10 11:20:29 martin Exp $");
+
+#ifdef _KERNEL_OPT
+#include "lapic.h"
+#endif
+
+#include <sys/param.h>
+
+#ifdef _KERNEL
+#include <sys/systm.h>
+#include <x86/cpuvar.h>
+#include <x86/apicvar.h>
+#include <machine/cpufunc.h>
+#include <machine/cputypes.h>
+#include <machine/specialreg.h>
+#else
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "cpuctl.h"
+#include "cpuctl_i386.h"
+#endif
+
+uint64_t
+cpu_tsc_freq_cpuid(struct cpu_info *ci)
+{
+       uint64_t freq = 0, khz;
+       uint32_t descs[4];
+       uint32_t denominator, numerator;
+
+       if (!((ci->ci_max_cpuid >= 0x15) && (cpu_vendor == CPUVENDOR_INTEL)))
+               return 0;
+               
+       x86_cpuid(0x15, descs);
+       denominator = descs[0];
+       numerator = descs[1];
+       if ((denominator != 0) && (numerator != 0)) {
+               khz = 0;
+               if (descs[2] != 0)
+                       khz = descs[2] / 1000;
+               else if (CPUID_TO_FAMILY(ci->ci_signature) == 6) {
+                       /*
+                        * Table 18-85 Nominal Core Crystal Clock Frequency,
+                        * 18.7.3 Determining the Processor Base Frequency,
+                        * Intel SDM.
+                        */
+                       switch (CPUID_TO_MODEL(ci->ci_signature)) {
+                       case 0x55: /* Xeon Scalable */
+                       case 0x5f: /*
+                                   * Atom Goldmont (Denverton). Right?
+                                   * XXX Not documented!
+                                   */
+                               khz = 25000; /* 25.0 MHz */
+                               break;
+                       case 0x4e: /* 7th gen Core (Skylake) */
+                       case 0x5e: /* 7th gen Core (Skylake) */
+                       case 0x8e: /* 8th gen Core (Kaby Lake) */
+                       case 0x9e: /* 8th gen Core (Kaby Lake) */
+                               khz = 24000; /* 24.0 MHz */
+                               break;
+                       case 0x5c: /* Atom Goldmont */
+                               khz = 19200; /* 19.2 MHz */
+                               break;
+                       default: /* Unknown */
+                               break;
+                       }
+               }
+               freq = khz * 1000 * numerator / denominator;
+               if (ci->ci_max_cpuid >= 0x16) {
+                       x86_cpuid(0x16, descs);
+                       if (descs[0] != 0) {
+                               aprint_verbose_dev(ci->ci_dev,
+                                   "CPU base freq %" PRIu64 " Hz\n",
+                                   (uint64_t)descs[0] * 1000000);
+
+                               /*
+                                * If we couldn't get frequency from
+                                * CPUID 0x15, use CPUID 0x16 EAX.
+                                */
+                               if (freq == 0) {
+                                       khz = (uint64_t)descs[0] * 1000
+                                           * denominator / numerator;
+                                       freq = (uint64_t)descs[0] * 1000000;
+                               }
+                       }
+                       if (descs[1] != 0) {
+                               aprint_verbose_dev(ci->ci_dev,
+                                   "CPU max freq %" PRIu64 " Hz\n",
+                                   (uint64_t)descs[1] * 1000000);
+                       }
+               }
+#if defined(_KERNEL) &&  NLAPIC > 0
+               if ((khz != 0) && (lapic_per_second == 0)) {
+                       lapic_per_second = khz * 1000;
+                       aprint_debug_dev(ci->ci_dev,
+                           "lapic_per_second set to %" PRIu32 "\n",
+                           lapic_per_second);
+               }
+#endif
+       }
+       if (freq != 0)
+               aprint_verbose_dev(ci->ci_dev, "TSC freq CPUID %" PRIu64
+                   " Hz\n", freq);
+
+       return freq;
+}
diff -r b333bc5a0244 -r 8d5332dd281e usr.sbin/cpuctl/Makefile
--- a/usr.sbin/cpuctl/Makefile  Fri Jul 10 10:45:56 2020 +0000
+++ b/usr.sbin/cpuctl/Makefile  Fri Jul 10 11:20:29 2020 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: Makefile,v 1.8 2016/01/23 21:22:50 christos Exp $
+#      $NetBSD: Makefile,v 1.8.18.1 2020/07/10 11:20:29 martin Exp $
 
 .include <bsd.own.mk>
 
@@ -19,6 +19,12 @@
 SRCS+= ${MACHINE_ARCH}-asm.S
 .endif
 
+.if ${MACHINE_ARCH} == "x86_64" || ${MACHINE_ARCH} == "i386"
+CPPFLAGS+= -I${.CURDIR} -I${.CURDIR}/arch
+.PATH.c: ${NETBSDSRCDIR}/sys/arch/x86/x86
+SRCS+= identcpu_subr.c
+.endif
+
 CPPFLAGS+=     -D_KERNTYPES
 LDADD+=-lutil
 DPADD+=${LIBUTIL}
diff -r b333bc5a0244 -r 8d5332dd281e usr.sbin/cpuctl/arch/cpuctl_i386.h
--- a/usr.sbin/cpuctl/arch/cpuctl_i386.h        Fri Jul 10 10:45:56 2020 +0000
+++ b/usr.sbin/cpuctl/arch/cpuctl_i386.h        Fri Jul 10 11:20:29 2020 +0000
@@ -1,4 +1,50 @@
-/*      $NetBSD: cpuctl_i386.h,v 1.4 2019/05/21 05:29:21 mlelstv Exp $      */
+/*      $NetBSD: cpuctl_i386.h,v 1.4.2.1 2020/07/10 11:20:29 martin Exp $      */
+
+#include <machine/specialreg.h>
+#include <x86/cputypes.h>
+#include <x86/cacheinfo.h>
+
+struct cpu_info {
+       const char      *ci_dev;
+       int32_t         ci_cpu_type;     /* for cpu's without cpuid */
+       uint32_t        ci_signature;    /* X86 cpuid type */
+       uint32_t        ci_vendor[4];    /* vendor string */
+       int32_t         ci_max_cpuid;    /* highest cpuid supported */
+       uint32_t        ci_max_ext_cpuid; /* highest cpuid extended func lv */
+       uint32_t        ci_family;       /* from ci_signature */
+       uint32_t        ci_model;        /* from ci_signature */
+       uint32_t        ci_feat_val[10]; /* X86 CPUID feature bits
+                                         *     [0] basic features %edx
+                                         *     [1] basic features %ecx
+                                         *     [2] extended features %edx
+                                         *     [3] extended features %ecx
+                                         *     [4] VIA padlock features
+                                         *     [5] structure ext. feat. %ebx
+                                         *     [6] structure ext. feat. %ecx
+                                         *     [7] structure ext. feat. %edx
+                                         *     [8] XCR0 bits (d:0 %eax)
+                                         *     [9] xsave flags (d:1 %eax)
+                                         */
+       uint32_t        ci_cpu_class;    /* CPU class */
+       uint32_t        ci_brand_id;     /* Intel brand id */
+       uint32_t        ci_cpu_serial[3]; /* PIII serial number */
+       uint64_t        ci_tsc_freq;     /* cpu cycles/second */
+       uint8_t         ci_packageid;
+       uint8_t         ci_coreid;
+       uint8_t         ci_smtid;
+       uint32_t        ci_initapicid;  /* our initial APIC ID */
+
+       uint32_t        ci_cur_xsave;
+       uint32_t        ci_max_xsave;
+
+       struct x86_cache_info ci_cinfo[CAI_COUNT];
+       void            (*ci_info)(struct cpu_info *);
+};
+
+extern int cpu_vendor;
+
+/* For x86/x86/identcpu_subr.c */
+uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
 
 /* Interfaces to code in i386-asm.S */
 
diff -r b333bc5a0244 -r 8d5332dd281e usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Fri Jul 10 10:45:56 2020 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Fri Jul 10 11:20:29 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $    */
+/*     $NetBSD: i386.c,v 1.104.2.6 2020/07/10 11:20:29 martin Exp $    */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.6 2020/07/10 11:20:29 martin Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -81,7 +81,6 @@
 
 #include <x86/cpuvar.h>
 #include <x86/cputypes.h>
-#include <x86/cacheinfo.h>
 #include <x86/cpu_ucode.h>
 
 #include "../cpuctl.h"
@@ -90,43 +89,6 @@
 /* Size of buffer for printing humanized numbers */
 #define HUMAN_BUFSIZE sizeof("999KB")
 
-struct cpu_info {
-       const char      *ci_dev;
-       int32_t         ci_cpu_type;     /* for cpu's without cpuid */
-       int32_t         ci_cpuid_level;  /* highest cpuid supported */
-       uint32_t        ci_cpuid_extlevel; /* highest cpuid extended func lv */
-       uint32_t        ci_signature;    /* X86 cpuid type */
-       uint32_t        ci_family;       /* from ci_signature */
-       uint32_t        ci_model;        /* from ci_signature */
-       uint32_t        ci_feat_val[10]; /* X86 CPUID feature bits
-                                         *     [0] basic features %edx
-                                         *     [1] basic features %ecx
-                                         *     [2] extended features %edx
-                                         *     [3] extended features %ecx
-                                         *     [4] VIA padlock features
-                                         *     [5] structure ext. feat. %ebx
-                                         *     [6] structure ext. feat. %ecx
-                                         *     [7] structure ext. feat. %edx
-                                         *     [8] XCR0 bits (d:0 %eax)
-                                         *     [9] xsave flags (d:1 %eax)
-                                         */
-       uint32_t        ci_cpu_class;    /* CPU class */
-       uint32_t        ci_brand_id;     /* Intel brand id */
-       uint32_t        ci_vendor[4];    /* vendor string */
-       uint32_t        ci_cpu_serial[3]; /* PIII serial number */
-       uint64_t        ci_tsc_freq;     /* cpu cycles/second */
-       uint8_t         ci_packageid;
-       uint8_t         ci_coreid;
-       uint8_t         ci_smtid;
-       uint32_t        ci_initapicid;
-
-       uint32_t        ci_cur_xsave;
-       uint32_t        ci_max_xsave;
-
-       struct x86_cache_info ci_cinfo[CAI_COUNT];
-       void            (*ci_info)(struct cpu_info *);
-};
-
 struct cpu_nocpuid_nameclass {
        int cpu_vendor;
        const char *cpu_vendorname;
@@ -197,7 +159,7 @@
        "4"             /* AMD Athlon(tm) 4 */
 };
 



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