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[src/trunk]: src/sys/external/bsd/drm2/dist/drm/i915 Avoid undefined behavior...



details:   https://anonhg.NetBSD.org/src/rev/a621bb2beff0
branches:  trunk
changeset: 964498:a621bb2beff0
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Aug 05 10:14:19 2019 +0000

description:
Avoid undefined behavior. Found by kUBSan.

diffstat:

 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h |  40 +++++++++++++-------------
 sys/external/bsd/drm2/dist/drm/i915/intel_pm.c |   6 +-
 2 files changed, 23 insertions(+), 23 deletions(-)

diffs (179 lines):

diff -r 481ed27c66ab -r a621bb2beff0 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h
--- a/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h    Mon Aug 05 10:12:04 2019 +0000
+++ b/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h    Mon Aug 05 10:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i915_reg.h,v 1.7 2019/07/24 15:55:07 msaitoh Exp $     */
+/*     $NetBSD: i915_reg.h,v 1.8 2019/08/05 10:14:19 msaitoh Exp $     */
 
 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
@@ -2225,7 +2225,7 @@
 #define   VGA1_PD_P1_DIV_2     (1 << 13)
 #define   VGA1_PD_P1_SHIFT     8
 #define   VGA1_PD_P1_MASK      (0x1f << 8)
-#define   DPLL_VCO_ENABLE              (1 << 31)
+#define   DPLL_VCO_ENABLE              __BIT(31)
 #define   DPLL_SDVO_HIGH_SPEED         (1 << 30)
 #define   DPLL_DVO_2X_MODE             (1 << 30)
 #define   DPLL_EXT_BUFFER_ENABLE_VLV   (1 << 30)
@@ -3175,7 +3175,7 @@
 #define PCH_ADPA                0xe1100
 #define VLV_ADPA               (VLV_DISPLAY_BASE + ADPA)
 
-#define   ADPA_DAC_ENABLE      (1<<31)
+#define   ADPA_DAC_ENABLE      __BIT(31)
 #define   ADPA_DAC_DISABLE     0
 #define   ADPA_PIPE_SELECT_MASK        (1<<30)
 #define   ADPA_PIPE_A_SELECT   0
@@ -3337,7 +3337,7 @@
 #define   PIPE_A_SCRAMBLE_RESET                        (1 << 0)
 
 /* Gen 3 SDVO bits: */
-#define   SDVO_ENABLE                          (1 << 31)
+#define   SDVO_ENABLE                          __BIT(31)
 #define   SDVO_PIPE_SEL(pipe)                  ((pipe) << 30)
 #define   SDVO_PIPE_SEL_MASK                   (1 << 30)
 #define   SDVO_PIPE_B_SELECT                   (1 << 30)
@@ -3428,7 +3428,7 @@
  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  * the DPLL semantics change when the LVDS is assigned to that pipe.
  */
-#define   LVDS_PORT_EN                 (1 << 31)
+#define   LVDS_PORT_EN                 (1U << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT            (1 << 30)
 #define   LVDS_PIPE_MASK               (1 << 30)
@@ -3588,7 +3588,7 @@
 
 /* Backlight control */
 #define BLC_PWM_CTL2   (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
-#define   BLM_PWM_ENABLE               (1 << 31)
+#define   BLM_PWM_ENABLE               __BIT(31)
 #define   BLM_COMBINATION_MODE         (1 << 30) /* gen4 only */
 #define   BLM_PIPE_SELECT              (1 << 29)
 #define   BLM_PIPE_SELECT_IVB          (3 << 29)
@@ -3645,7 +3645,7 @@
 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
 #define BLC_PWM_PCH_CTL1       0xc8250
-#define   BLM_PCH_PWM_ENABLE                   (1 << 31)
+#define   BLM_PCH_PWM_ENABLE                   __BIT(31)
 #define   BLM_PCH_OVERRIDE_ENABLE              (1 << 30)
 #define   BLM_PCH_POLARITY                     (1 << 29)
 #define BLC_PWM_PCH_CTL2       0xc8254
@@ -4166,7 +4166,7 @@
 #define VLV_DP_C                       (VLV_DISPLAY_BASE + DP_C)
 #define CHV_DP_D                       (VLV_DISPLAY_BASE + DP_D)
 
-#define   DP_PORT_EN                   (1 << 31)
+#define   DP_PORT_EN                   __BIT(31)
 #define   DP_PIPEB_SELECT              (1 << 30)
 #define   DP_PIPE_MASK                 (1 << 30)
 #define   DP_PIPE_SELECT_CHV(pipe)     ((pipe) << 16)
@@ -5052,7 +5052,7 @@
 
 /* Sprite A control */
 #define _DVSACNTR              0x72180
-#define   DVS_ENABLE           (1<<31)
+#define   DVS_ENABLE           __BIT(31)
 #define   DVS_GAMMA_ENABLE     (1<<30)
 #define   DVS_PIXFORMAT_MASK   (3<<25)
 #define   DVS_FORMAT_YUV422    (0<<25)
@@ -5459,7 +5459,7 @@
 
 /* VBIOS regs */
 #define VGACNTRL               0x71400
-# define VGA_DISP_DISABLE                      (1 << 31)
+# define VGA_DISP_DISABLE                      __BIT(31)
 # define VGA_2X_MODE                           (1 << 30)
 # define VGA_PIPE_B_SELECT                     (1 << 29)
 
@@ -6367,7 +6367,7 @@
 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
 #define LPT_TRANSCONF          _PCH_TRANSACONF /* lpt has only one transcoder */
 #define  TRANS_DISABLE          (0<<31)
-#define  TRANS_ENABLE           (1<<31)
+#define  TRANS_ENABLE           __BIT(31)
 #define  TRANS_STATE_MASK       (1<<30)
 #define  TRANS_STATE_DISABLE    (0<<30)
 #define  TRANS_STATE_ENABLE     (1<<30)
@@ -6392,7 +6392,7 @@
 #define _TRANSA_CHICKEN2        0xf0064
 #define _TRANSB_CHICKEN2        0xf1064
 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define  TRANS_CHICKEN2_TIMING_OVERRIDE                        (1<<31)
+#define  TRANS_CHICKEN2_TIMING_OVERRIDE                        __BIT(31)
 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED          (1<<29)
 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK         (3<<27)
 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER     (1<<26)
@@ -6428,7 +6428,7 @@
 #define _FDI_TXB_CTL             0x61100
 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
 #define  FDI_TX_DISABLE         (0<<31)
-#define  FDI_TX_ENABLE          (1<<31)
+#define  FDI_TX_ENABLE          __BIT(31)
 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
 #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
@@ -6477,7 +6477,7 @@
 #define _FDI_RXA_CTL             0xf000c
 #define _FDI_RXB_CTL             0xf100c
 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
-#define  FDI_RX_ENABLE          (1<<31)
+#define  FDI_RX_ENABLE          __BIT(31)
 /* train, dp width same as FDI_TX */
 #define  FDI_FS_ERRC_ENABLE            (1<<27)
 #define  FDI_FE_ERRC_ENABLE            (1<<26)
@@ -6582,11 +6582,11 @@
 #define  PANEL_POWER_OFF       (0 << 0)
 #define  PANEL_POWER_ON                (1 << 0)
 #define PCH_PP_ON_DELAYS       0xc7208
-#define  PANEL_PORT_SELECT_MASK        (3 << 30)
-#define  PANEL_PORT_SELECT_LVDS        (0 << 30)
-#define  PANEL_PORT_SELECT_DPA (1 << 30)
-#define  PANEL_PORT_SELECT_DPC (2 << 30)
-#define  PANEL_PORT_SELECT_DPD (3 << 30)
+#define  PANEL_PORT_SELECT_MASK        (3U << 30)
+#define  PANEL_PORT_SELECT_LVDS        (0U << 30)
+#define  PANEL_PORT_SELECT_DPA (1U << 30)
+#define  PANEL_PORT_SELECT_DPC (2U << 30)
+#define  PANEL_PORT_SELECT_DPD (3U << 30)
 #define  PANEL_POWER_UP_DELAY_MASK     (0x1fff0000)
 #define  PANEL_POWER_UP_DELAY_SHIFT    16
 #define  PANEL_LIGHT_ON_DELAY_MASK     (0x1fff)
@@ -6654,7 +6654,7 @@
 #define TRANS_DP_CTL_B         0xe1300
 #define TRANS_DP_CTL_C         0xe2300
 #define TRANS_DP_CTL(pipe)     _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
-#define  TRANS_DP_OUTPUT_ENABLE        (1<<31)
+#define  TRANS_DP_OUTPUT_ENABLE        __BIT(31)
 #define  TRANS_DP_PORT_SEL_B   (0<<29)
 #define  TRANS_DP_PORT_SEL_C   (1<<29)
 #define  TRANS_DP_PORT_SEL_D   (2<<29)
diff -r 481ed27c66ab -r a621bb2beff0 sys/external/bsd/drm2/dist/drm/i915/intel_pm.c
--- a/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c    Mon Aug 05 10:12:04 2019 +0000
+++ b/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c    Mon Aug 05 10:14:19 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intel_pm.c,v 1.17 2019/07/24 14:57:09 msaitoh Exp $    */
+/*     $NetBSD: intel_pm.c,v 1.18 2019/08/05 10:14:19 msaitoh Exp $    */
 
 /*
  * Copyright © 2012 Intel Corporation
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.17 2019/07/24 14:57:09 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.18 2019/08/05 10:14:19 msaitoh Exp $");
 
 #include <linux/bitops.h>
 #include <linux/cpufreq.h>
@@ -5036,7 +5036,7 @@
                DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
 
        ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
-       if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
+       if (!ret && (pcu_mbox & __BIT(31))) { /* OC supported */
                DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
                                 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
                                 (pcu_mbox & 0xff) * 50);



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