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[src/netbsd-9]: src/sys/dev Pull up following revision(s) (requested by msait...



details:   https://anonhg.NetBSD.org/src/rev/b76adfcc9a6e
branches:  netbsd-9
changeset: 964053:b76adfcc9a6e
user:      martin <martin%NetBSD.org@localhost>
date:      Wed Aug 05 15:14:18 2020 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #1040):

        sys/dev/mii/igphy.c: revision 1.35
        sys/dev/mii/igphy.c: revision 1.36
        sys/dev/mii/igphyreg.h: revision 1.12
        sys/dev/mii/igphyreg.h: revision 1.13
        sys/dev/mii/makphyreg.h: revision 1.11
        sys/dev/pci/if_wm.c: revision 1.682
        sys/dev/pci/if_wm.c: revision 1.683
        sys/dev/pci/if_wm.c: revision 1.684
        sys/dev/pci/if_wm.c: revision 1.685
        sys/dev/mii/makphy.c: revision 1.66

s/MII_IGPHY_/IGPHY_/. No functional change.

Rename PSSR_* to MAKPHY_PSSR_* and IGPHY_PSSR_* to avoid conflict.
No functional change.

  Setup PCS and SGMII for SFP correctly. It still doesn't support SFP
insertion/removal.

Copper:
wm2: SGMII(SFP)
wm2: 0x1043c440<SPI,IOH_VALID,PCIE,SGMII,NEWQUEUE,ASF_FIRM,EEE,SFP>
makphy0 at wm2 phy 6: Marvell 88E1111 Gigabit PHY, rev. 1

Fiber:
wm3: SERDES(SFP)
wm3: 0x10034440<SPI,IOH_VALID,PCIE,NEWQUEUE,ASF_FIRM,SFP>
wm3: 1000baseSX, 1000baseSX-FDX, auto

  Explicitly cast from uint16_t to uint32_t before shifting 16bit left
when printing Image Unique ID. Found by kUBSan.

  Set if_baudrate for non-MII device. Before this commit, it was 0.

diffstat:

 sys/dev/mii/igphy.c     |  38 +++++++++---------
 sys/dev/mii/igphyreg.h  |  96 ++++++++++++++++++++++++------------------------
 sys/dev/mii/makphy.c    |  18 ++++----
 sys/dev/mii/makphyreg.h |  28 +++++++-------
 sys/dev/pci/if_wm.c     |  80 +++++++++++++++++++++++++++++++---------
 5 files changed, 152 insertions(+), 108 deletions(-)

diffs (truncated from 667 to 300 lines):

diff -r c19bf01ed7f3 -r b76adfcc9a6e sys/dev/mii/igphy.c
--- a/sys/dev/mii/igphy.c       Wed Aug 05 15:06:55 2020 +0000
+++ b/sys/dev/mii/igphy.c       Wed Aug 05 15:14:18 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: igphy.c,v 1.31 2019/03/25 07:34:13 msaitoh Exp $       */
+/*     $NetBSD: igphy.c,v 1.31.4.1 2020/08/05 15:14:18 martin Exp $    */
 
 /*
  * The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.31 2019/03/25 07:34:13 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.31.4.1 2020/08/05 15:14:18 martin Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_mii.h"
@@ -270,7 +270,7 @@
 
        delay(20000);
 
-       PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+       PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
        PHY_WRITE(sc, 0x0000, 0x0140);
 
        delay(5000);
@@ -278,7 +278,7 @@
        for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
                IGPHY_WRITE(sc, code[i].reg, code[i].val);
 
-       PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+       PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
        PHY_WRITE(sc, 0x0000, 0x3300);
 
        delay(20000);
@@ -323,9 +323,9 @@
        }
 
        if (igsc->sc_mactype == WM_T_82547) {
-               IGPHY_READ(sc, MII_IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
+               IGPHY_READ(sc, IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
                if ((fused & ANALOG_SPARE_FUSE_ENABLED) == 0) {
-                       IGPHY_READ(sc, MII_IGPHY_ANALOG_FUSE_STATUS, &fused);
+                       IGPHY_READ(sc, IGPHY_ANALOG_FUSE_STATUS, &fused);
 
                        fine = fused & ANALOG_FUSE_FINE_MASK;
                        coarse = fused & ANALOG_FUSE_COARSE_MASK;
@@ -340,12 +340,12 @@
                            (fine & ANALOG_FUSE_FINE_MASK) |
                            (coarse & ANALOG_FUSE_COARSE_MASK);
 
-                       IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_CONTROL, fused);
-                       IGPHY_WRITE(sc, MII_IGPHY_ANALOG_FUSE_BYPASS,
+                       IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_CONTROL, fused);
+                       IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_BYPASS,
                            ANALOG_FUSE_ENABLE_SW_CONTROL);
                }
        }
-       PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, 0x0000);
+       PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
 }
 
 
@@ -377,14 +377,14 @@
                if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
                        break;
 
-               PHY_READ(sc, MII_IGPHY_PORT_CTRL, &reg);
+               PHY_READ(sc, IGPHY_PORT_CTRL, &reg);
                if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
                        reg |= PSCR_AUTO_MDIX;
                        reg &= ~PSCR_FORCE_MDI_MDIX;
-                       PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+                       PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
                } else {
                        reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);
-                       PHY_WRITE(sc, MII_IGPHY_PORT_CTRL, reg);
+                       PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
                }
 
                mii_phy_setmedia(sc);
@@ -425,9 +425,9 @@
        mii->mii_media_status = IFM_AVALID;
        mii->mii_media_active = IFM_ETHER;
 
-       PHY_READ(sc, MII_IGPHY_PORT_STATUS, &pssr);
+       PHY_READ(sc, IGPHY_PORT_STATUS, &pssr);
 
-       if (pssr & PSSR_LINK_UP)
+       if (pssr & IGPHY_PSSR_LINK_UP)
                mii->mii_media_status |= IFM_ACTIVE;
 
        PHY_READ(sc, MII_BMCR, &bmcr);
@@ -449,19 +449,19 @@
                        mii->mii_media_active |= IFM_NONE;
                        return;
                }
-               switch (pssr & PSSR_SPEED_MASK) {
-               case PSSR_SPEED_1000MBPS:
+               switch (pssr & IGPHY_PSSR_SPEED_MASK) {
+               case IGPHY_PSSR_SPEED_1000MBPS:
                        mii->mii_media_active |= IFM_1000_T;
                        PHY_READ(sc, MII_100T2SR, &gtsr);
                        if (gtsr & GTSR_MS_RES)
                                mii->mii_media_active |= IFM_ETH_MASTER;
                        break;
 
-               case PSSR_SPEED_100MBPS:
+               case IGPHY_PSSR_SPEED_100MBPS:
                        mii->mii_media_active |= IFM_100_TX;
                        break;
 
-               case PSSR_SPEED_10MBPS:
+               case IGPHY_PSSR_SPEED_10MBPS:
                        mii->mii_media_active |= IFM_10_T;
                        break;
 
@@ -471,7 +471,7 @@
                        return;
                }
 
-               if (pssr & PSSR_FULL_DUPLEX)
+               if (pssr & IGPHY_PSSR_FULL_DUPLEX)
                        mii->mii_media_active |=
                            IFM_FDX | mii_phy_flowstatus(sc);
                else
diff -r c19bf01ed7f3 -r b76adfcc9a6e sys/dev/mii/igphyreg.h
--- a/sys/dev/mii/igphyreg.h    Wed Aug 05 15:06:55 2020 +0000
+++ b/sys/dev/mii/igphyreg.h    Wed Aug 05 15:14:18 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: igphyreg.h,v 1.11 2019/01/22 03:42:27 msaitoh Exp $    */
+/*     $NetBSD: igphyreg.h,v 1.11.4.1 2020/08/05 15:14:18 martin Exp $ */
 
 /*******************************************************************************
 
@@ -43,7 +43,7 @@
  */
 
 /* IGP01E1000 Specific Port Config Register - R/W */
-#define MII_IGPHY_PORT_CONFIG          0x10 /* PHY specific config register */
+#define IGPHY_PORT_CONFIG              0x10 /* PHY specific config register */
 #define PSCFR_AUTO_MDIX_PAR_DETECT     0x0010
 #define PSCFR_PRE_EN                   0x0020
 #define PSCFR_SMART_SPEED              0x0080
@@ -52,22 +52,22 @@
 #define PSCFR_DISABLE_TRANSMIT         0x2000
 
 /* IGP01E1000 Specific Port Status Register - R/O */
-#define MII_IGPHY_PORT_STATUS          0x11
-#define PSSR_AUTONEG_FAILED            0x0001 /* RO LH SC */
-#define PSSR_POLARITY_REVERSED         0x0002
-#define PSSR_CABLE_LENGTH              0x007C
-#define PSSR_FULL_DUPLEX               0x0200
-#define PSSR_LINK_UP                   0x0400
-#define PSSR_MDIX                      0x0800
-#define PSSR_SPEED_MASK                        0xC000 /* speed bits mask */
-#define PSSR_SPEED_10MBPS              0x4000
-#define PSSR_SPEED_100MBPS             0x8000
-#define PSSR_SPEED_1000MBPS            0xC000
-#define PSSR_CABLE_LENGTH_SHIFT        0x0002 /* shift right 2 */
-#define PSSR_MDIX_SHIFT                        0x000B /* shift right 11 */
+#define IGPHY_PORT_STATUS              0x11
+#define IGPHY_PSSR_AUTONEG_FAILED      0x0001 /* RO LH SC */
+#define IGPHY_PSSR_POLARITY_REVERSED   0x0002
+#define IGPHY_PSSR_CABLE_LENGTH                0x007C
+#define IGPHY_PSSR_FULL_DUPLEX         0x0200
+#define IGPHY_PSSR_LINK_UP             0x0400
+#define IGPHY_PSSR_MDIX                        0x0800
+#define IGPHY_PSSR_SPEED_MASK          0xC000 /* speed bits mask */
+#define IGPHY_PSSR_SPEED_10MBPS                0x4000
+#define IGPHY_PSSR_SPEED_100MBPS       0x8000
+#define IGPHY_PSSR_SPEED_1000MBPS      0xC000
+#define IGPHY_PSSR_CABLE_LENGTH_SHIFT  0x0002 /* shift right 2 */
+#define IGPHY_PSSR_MDIX_SHIFT          0x000B /* shift right 11 */
 
 /* IGP01E1000 Specific Port Control Register - R/W */
-#define MII_IGPHY_PORT_CTRL            0x12
+#define IGPHY_PORT_CTRL                        0x12
 #define PSCR_TP_LOOPBACK               0x0010
 #define PSCR_CORRECT_NC_SCMBLR         0x0200
 #define PSCR_TEN_CRS_SELECT            0x0400
@@ -76,7 +76,7 @@
 #define PSCR_FORCE_MDI_MDIX            0x2000 /* 0-MDI, 1-MDIX */
 
 /* IGP01E1000 Specific Port Link Health Register */
-#define MII_IGPHY_LINK_HEALTH          0x13
+#define IGPHY_LINK_HEALTH              0x13
 #define PLHR_VALID_CHANNEL_A           0x0001
 #define PLHR_VALID_CHANNEL_B           0x0002
 #define PLHR_VALID_CHANNEL_C           0x0004
@@ -96,61 +96,61 @@
 #define GMII_SPD                       0x20 /* Enable SPD */
 
 /* IGP01E1000 Channel Quality Register */
-#define MII_IGPHY_CHANNEL_QUALITY      0x15
+#define IGPHY_CHANNEL_QUALITY          0x15
 #define MSE_CHANNEL_A                  0x000F
 #define MSE_CHANNEL_B                  0x00F0
 #define MSE_CHANNEL_C                  0x0F00
 #define MSE_CHANNEL_D                  0xF000
 
 /* IGP01E1000 Power Management */
-#define MII_IGPHY_POWER_MGMT           0x19
+#define IGPHY_POWER_MGMT               0x19
 #define PMR_SPD_EN                     0x0001
 #define PMR_D0_LPLU                    0x0002
 #define PMR_D3_LPLU                    0x0004
 #define PMR_DIS_1000                   0x0040
 
-#define MII_IGPHY_PAGE_SELECT          0x1F
+#define IGPHY_PAGE_SELECT              0x1F
 #define IGPHY_MAXREGADDR               0x1F
 #define IGPHY_PAGEMASK                 (~IGPHY_MAXREGADDR)
 
 /* IGP01E1000 AGC Registers - stores the cable length values*/
-#define MII_IGPHY_AGC_A                        0x1172
-#define MII_IGPHY_AGC_PARAM_A          0x1171
-#define MII_IGPHY_AGC_B                        0x1272
-#define MII_IGPHY_AGC_PARAM_B          0x1271
-#define MII_IGPHY_AGC_C                        0x1472
-#define MII_IGPHY_AGC_PARAM_C          0x1471
-#define MII_IGPHY_AGC_D                        0x1872
-#define MII_IGPHY_AGC_PARAM_D          0x1871
+#define IGPHY_AGC_A                    0x1172
+#define IGPHY_AGC_PARAM_A              0x1171
+#define IGPHY_AGC_B                    0x1272
+#define IGPHY_AGC_PARAM_B              0x1271
+#define IGPHY_AGC_C                    0x1472
+#define IGPHY_AGC_PARAM_C              0x1471
+#define IGPHY_AGC_D                    0x1872
+#define IGPHY_AGC_PARAM_D              0x1871
 #define AGC_LENGTH_SHIFT               7  /* Coarse - 13:11, Fine - 10:7 */
 #define AGC_LENGTH_TABLE_SIZE          128
 #define AGC_RANGE                      10
 
 /* IGP01E1000 DSP Reset Register */
-#define MII_IGPHY_DSP_RESET            0x1F33
-#define MII_IGPHY_DSP_SET              0x1F71
-#define MII_IGPHY_DSP_FFE              0x1F35
-#define MII_IGPHY_CHANNEL_NUM          4
-#define MII_IGPHY_EDAC_MU_INDEX                0xC000
-#define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000
-#define MII_IGPHY_ANALOG_TX_STATE      0x2890
-#define MII_IGPHY_ANALOG_CLASS_A       0x2000
-#define MII_IGPHY_FORCE_ANALOG_ENABLE  0x0004
-#define MII_IGPHY_DSP_FFE_CM_CP                0x0069
-#define MII_IGPHY_DSP_FFE_DEFAULT      0x002A
+#define IGPHY_DSP_RESET                        0x1F33
+#define IGPHY_DSP_SET                  0x1F71
+#define IGPHY_DSP_FFE                  0x1F35
+#define IGPHY_CHANNEL_NUM              4
+#define IGPHY_EDAC_MU_INDEX            0xC000
+#define IGPHY_EDAC_SIGN_EXT_9_BITS     0x8000
+#define IGPHY_ANALOG_TX_STATE          0x2890
+#define IGPHY_ANALOG_CLASS_A           0x2000
+#define IGPHY_FORCE_ANALOG_ENABLE      0x0004
+#define IGPHY_DSP_FFE_CM_CP            0x0069
+#define IGPHY_DSP_FFE_DEFAULT          0x002A
 
 /* IGP01E1000 PCS Initialization register - stores the polarity status */
-#define MII_IGPHY_PCS_INIT_REG         0x00B4
-#define MII_IGPHY_PCS_CTRL_REG         0x00B5
+#define IGPHY_PCS_INIT_REG             0x00B4
+#define IGPHY_PCS_CTRL_REG             0x00B5
 
-#define MII_IGPHY_ANALOG_REGS_PAGE     0x20C0
+#define IGPHY_ANALOG_REGS_PAGE         0x20C0
 #define PHY_POLARITY_MASK              0x0078
 
 /* IGP01E1000 Analog Register */
-#define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS     0x20D1
-#define MII_IGPHY_ANALOG_FUSE_STATUS           0x20D0
-#define MII_IGPHY_ANALOG_FUSE_CONTROL          0x20DC
-#define MII_IGPHY_ANALOG_FUSE_BYPASS           0x20DE
+#define IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1
+#define IGPHY_ANALOG_FUSE_STATUS       0x20D0
+#define IGPHY_ANALOG_FUSE_CONTROL      0x20DC
+#define IGPHY_ANALOG_FUSE_BYPASS       0x20DE
 #define ANALOG_FUSE_POLY_MASK          0xF000
 #define ANALOG_FUSE_FINE_MASK          0x0F80
 #define ANALOG_FUSE_COARSE_MASK                0x0070
@@ -180,7 +180,7 @@
 {
        int rv;
 
-       if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+       if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
                return rv;
        return PHY_READ(sc, reg & 0x1f, val);
 }
@@ -189,7 +189,7 @@
 {
        int rv;
 
-       if ((rv = PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
+       if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
                return rv;
 
        return PHY_WRITE(sc, reg & 0x1f, val);



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