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[src/trunk]: src/sys/arch/acorn32/stand Modernize acorn32 boot code to work d...



details:   https://anonhg.NetBSD.org/src/rev/89bce931edd1
branches:  trunk
changeset: 951588:89bce931edd1
user:      joerg <joerg%NetBSD.org@localhost>
date:      Sat Feb 06 21:45:38 2021 +0000

description:
Modernize acorn32 boot code to work directly with LLVM's assembler.

diffstat:

 sys/arch/acorn32/stand/boot32/Makefile |   4 +---
 sys/arch/acorn32/stand/boot32/start.S  |  34 +++++++++++++++++-----------------
 sys/arch/acorn32/stand/nbfs/Makefile   |   4 +---
 sys/arch/acorn32/stand/nbfs/rmheader.S |  14 ++++++++------
 4 files changed, 27 insertions(+), 29 deletions(-)

diffs (181 lines):

diff -r f9cbf4d2fe68 -r 89bce931edd1 sys/arch/acorn32/stand/boot32/Makefile
--- a/sys/arch/acorn32/stand/boot32/Makefile    Sat Feb 06 21:40:14 2021 +0000
+++ b/sys/arch/acorn32/stand/boot32/Makefile    Sat Feb 06 21:45:38 2021 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: Makefile,v 1.6 2019/08/02 12:06:20 joerg Exp $
+#      $NetBSD: Makefile,v 1.7 2021/02/06 21:45:38 joerg Exp $
 
 PROG=          boot32
 PROGSOURCE=    rmheader.S rmvers.c srt0.S boot32.c start.S
@@ -17,6 +17,4 @@
 
 CLEANFILES+=   rmvers.c
 
-AFLAGS.start.S= ${${ACTIVE_CC} == "clang":?-no-integrated-as:}
-
 .include "../Makefile.buildboot"
diff -r f9cbf4d2fe68 -r 89bce931edd1 sys/arch/acorn32/stand/boot32/start.S
--- a/sys/arch/acorn32/stand/boot32/start.S     Sat Feb 06 21:40:14 2021 +0000
+++ b/sys/arch/acorn32/stand/boot32/start.S     Sat Feb 06 21:45:38 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: start.S,v 1.3 2008/02/03 14:59:16 chris Exp $  */
+/*     $NetBSD: start.S,v 1.4 2021/02/06 21:45:38 joerg Exp $  */
 
 /*
  * Copyright (c) 2002 Reinoud Zandijk
@@ -50,7 +50,7 @@
         * determine processor architecture version. This is nessisary for the
         * correct coprocessor instruction.
         */
-       mrc     15, 0, r0, c0, c0, 0                                    /* read CPU id in r0                    */
+       mrc     p15, 0, r0, c0, c0, 0                                   /* read CPU id in r0                    */
        mov     r3, r0                                                  /* store in r3                          */
 
        /* assume its ARMv4 instruction set                                                                     */
@@ -77,23 +77,23 @@
        /* flush ID cache                                                                                       */
        mov     r0, #0
        cmp     r14, #0
-       mcreq   15, 0, r0, c7, c0, 0                                    /* flush v3 ID cache                    */
-       mcrne   15, 0, r0, c7, c7, 0                                    /* flush v4 ID cache                    */
-       mcrne   15, 0, r0, c7, c10, 4                                   /* drain WB (v4)                        */
+       mcreq   p15, 0, r0, c7, c0, 0                                   /* flush v3 ID cache                    */
+       mcrne   p15, 0, r0, c7, c7, 0                                   /* flush v4 ID cache                    */
+       mcrne   p15, 0, r0, c7, c10, 4                                  /* drain WB (v4)                        */
 
        /* flush TLB                                                                                            */
-       mcr     15, 0, r0, c5, c0, 0                                    /* flush TLB for v3 and v4              */
+       mcr     p15, 0, r0, c5, c0, 0                                   /* flush TLB for v3 and v4              */
 
        /* switch off MMU, IDcache and WB and branch to physical code space                                     */
        cmp     r14, #0
-       mrcne   15, 0, r0, c1, c0, 0                                    /* read processor control register if v4*/
+       mrcne   p15, 0, r0, c1, c0, 0                                   /* read processor control register if v4*/
        bic     r0, r0, #0x3f                                           /* clear only known bits                */
        moveq   r0, #0                                                  /* for v3 just set to zero              */
        orr     r0, r0, #CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_32BP_ENABLE
        mov     r13, r0                                                 /* save this control value in r13       */
        cmp     r14, #0
-       mcr     15, 0, r0, c1, c0, 0                                    /* write control register!              */
-/*1*/  mcrne   15, 0, r1, c7, c5, 0                                    /* write zero in ARMv4 MMU disable      */
+       mcr     p15, 0, r0, c1, c0, 0                                   /* write control register!              */
+/*1*/  mcrne   p15, 0, r1, c7, c5, 0                                   /* write zero in ARMv4 MMU disable      */
 /*2*/  mov     pc, r9                                                  /* branch to physical address           */      
        
 relocate_code_physical_restart:
@@ -132,25 +132,25 @@
        /* flush ID cache                                                                                       */
        mov     r0, #0
        cmp     r14, #0
-       mcreq   15, 0, r0, c7, c0, 0                                    /* flush v3 ID cache                    */
-       mcrne   15, 0, r0, c7, c7, 0                                    /* flush v4 ID cache                    */
+       mcreq   p15, 0, r0, c7, c0, 0                                   /* flush v3 ID cache                    */
+       mcrne   p15, 0, r0, c7, c7, 0                                   /* flush v4 ID cache                    */
 
        /* drain write buffer (v4)                                                                              */
        mov     r0, #0
        cmp     r14, #0
-       mcrne   15, 0, r0, c7, c10, 4                                   /* drain WB (v4)                        */
+       mcrne   p15, 0, r0, c7, c10, 4                                  /* drain WB (v4)                        */
 
        /* flush TLB                                                                                            */
-       mcr     15, 0, r0, c5, c0, 0                                    /* flush TLB for v3 and v4              */
+       mcr     p15, 0, r0, c5, c0, 0                                   /* flush TLB for v3 and v4              */
 
        /* set new TLB address                                                                                  */
        mov     r0, r11
-       mcr     15, 0, r0, c2, c0, 0                                    /* write TLB address                    */
+       mcr     p15, 0, r0, c2, c0, 0                                   /* write TLB address                    */
 
        /* Switch on MMU, IDCache and WB and keep on running on flat translated memory                          */
        orr     r0, r13, #CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_32BP_ENABLE
        orr     r0, r0,  #CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_DC_ENABLE   | CPU_CONTROL_MMU_ENABLE
-       mcr     15, 0, r0, c1, c0, 0                                    /* write register !!!                   */
+       mcr     p15, 0, r0, c1, c0, 0                                   /* write register !!!                   */
        mov     r0, r0                                                  /* flat                                 */
        mov     r0, r0                                                  /* flat                                 */
        /* not flat anymore but we just continue                                                                */
@@ -196,7 +196,7 @@
 
        /* relocate the relocation routine to the given page */
        adr     r6, relocate_code
-       mov     r7, #relocate_table_start - relocate_code       /* get length to copy */
+       ldr     r7, =relocate_table_start - relocate_code       /* get length to copy */
        mov     r8, r0
 relocate_code_loop:
        ldr     r9, [r6], #4
@@ -242,7 +242,7 @@
 
        /* set up info */
        mov     r9, r0                                                  /* save relocated page address          */
-       mov     r7, #relocate_code_physical_restart - relocate_code     /* get offset                           */
+       ldr     r7, =relocate_code_physical_restart - relocate_code     /* get offset                   */
        add     r1, r0, r1                                              /* get physical address                 */
        add     r1, r1, r7                                              /* add offset                           */
        mov     r0, r2                                                  /* put configuration structure in r0    */
diff -r f9cbf4d2fe68 -r 89bce931edd1 sys/arch/acorn32/stand/nbfs/Makefile
--- a/sys/arch/acorn32/stand/nbfs/Makefile      Sat Feb 06 21:40:14 2021 +0000
+++ b/sys/arch/acorn32/stand/nbfs/Makefile      Sat Feb 06 21:45:38 2021 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: Makefile,v 1.4 2019/08/02 12:06:20 joerg Exp $
+#      $NetBSD: Makefile,v 1.5 2021/02/06 21:45:38 joerg Exp $
 
 PROG=          nbfs
 PROGSOURCE=    rmheader.S rmvers.c nbfs.c rmalloc.c
@@ -13,6 +13,4 @@
 
 CLEANFILES+=   rmvers.c
 
-AFLAGS.rmheader.S= ${${ACTIVE_CC} == "clang":?-no-integrated-as:}
-
 .include "../Makefile.buildboot"
diff -r f9cbf4d2fe68 -r 89bce931edd1 sys/arch/acorn32/stand/nbfs/rmheader.S
--- a/sys/arch/acorn32/stand/nbfs/rmheader.S    Sat Feb 06 21:40:14 2021 +0000
+++ b/sys/arch/acorn32/stand/nbfs/rmheader.S    Sat Feb 06 21:45:38 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: rmheader.S,v 1.4 2006/07/13 16:09:58 bjh21 Exp $       */
+/*     $NetBSD: rmheader.S,v 1.5 2021/02/06 21:45:38 joerg Exp $       */
 
 /*-
  * Copyright (c) 2001, 2006 Ben Harris
@@ -36,6 +36,8 @@
 
 #include "nbfs.h"
 
+.syntax unified
+
 rmbase:
        .word   0                       /* Start code */
        .word   rminit - rmbase         /* Initialisation code */
@@ -97,7 +99,7 @@
        stmfd   r13!, {r14}
        mov     r0, #OSFSControl_AddFS
        adr     r1, rmbase
-       mov     r2, #(fsib - rmbase)
+       ldr     r2, =(fsib - rmbase)
        mov     r3, #0
        swi     XOS_FSControl
        ldmfd   r13!, {pc}              /* If that failed, so do we */
@@ -119,8 +121,8 @@
        
 Lerror:
        teq     pc, pc                  /* In 26-bit mode? */
-       ldmneia r13!, {r14}             /* If so, load up return address */
-       orrnes  pc, r14, #R15_FLAG_V    /* and return setting V flag */
+       ldmfdne r13!, {r14}             /* If so, load up return address */
+       orrsne  pc, r14, #R15_FLAG_V    /* and return setting V flag */
        mrs     r14, cpsr               /* Otherwise get cpsr */
        orr     r14, r14, #PSR_V_bit    /* set V flag */
        msr     cpsr_c, r14             /* put it back */
@@ -176,9 +178,9 @@
 
 fsentry_ret:
        cmp     r0, #0
-       ldmeqfd r13!, {r0-r7, pc}
+       popeq   {r0-r7, pc}
        add     r13, r13, #4
-       ldmfd   r13!, {r1-r7}
+       pop     {r1-r7}
        b       Lerror
 
 rmcmdtbl:



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